Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Scot H. Rider"'
Autor:
Jinwook Oh, Alyssa Herbert, Marcel Schaal, Zhibin Ren, Ching Zhou, Siyu Koswatta, Naigang Wang, Matthew Cohen, Vidhi Zalani, Howard M. Haynie, Matthew M. Ziegler, Sae Kyu Lee, Brian W. Curran, Monodeep Kar, Martin Lutz, Xin Zhang, Robert Casatuta, Vijayalakshmi Srinivasan, Nianzheng Cao, Sunil Shukla, Pong-Fei Lu, Leland Chang, Michael A. Guillorn, Bruce M. Fleischer, Michael R. Scheuermann, Joel Abraham Silberman, Kerstin Schelm, Vinay Velji Shah, Chia-Yu Chen, Kailash Gopalakrishnan, Swagath Venkataramani, Hung Tran, Mingu Kang, Wei Wang, Jungwook Choi, Scot H. Rider, Jinwook Jung, James J. Bonanno, Radhika Jain, Li Yulong, Xiao Sun, Silvia Melitta Mueller, Kyu-hyoun Kim, Ankur Agrawal
Publikováno v:
IEEE Journal of Solid-State Circuits. 57:182-197
Reduced precision computation is a key enabling factor for energy-efficient acceleration of deep learning (DL) applications. This article presents a 7-nm four-core mixed-precision artificial intelligence (AI) chip that supports four compute precision
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2998556a11fb9c2dbdc4775ef363b4bb
https://doi.org/10.1109/jssc.2021.3120113
https://doi.org/10.1109/jssc.2021.3120113
Autor:
Scot H. Rider, Martin Lutz, Moriyoshi Ohara, Pong-Fei Lu, Monodeep Kar, Xiao Sun, Kailash Gopalakrishnan, Jie Yang, Hoang Tran, Wei Wang, Michael A. Guillorn, Marcel Schaal, Ankur Agrawal, Xin Zhang, Joel Abraham Silberman, Sunil Shukla, Nianzheng Cao, James Bonano, Zhibin Ren, Sanchari Sen, Siyu Koswatta, Kyu-hyoun Kim, Mingu Kang, Swagath Venkataramani, Eri Ogawa, Vijayalakshmi Srinivasan, Hiroshi Inoue, Matt Ziegler, Howard M. Haynie, Shubham Jain, Vinay Velji Shah, Allison Allain, Jintao Zhang, Matthew Cohen, Jungwook Choi, Kerstin Schelm, Jinwook Oh, Li Yulong, Chia-Yu Chen, Ching Zhou, Naigang Wang, Jinwook Jung, Sae Kyu Lee, Silvia Melitta Mueller, Kazuaki Ishizaki, Bruce M. Fleischer, Michael R. Scheuermann, Vidhi Zalani, Brian W. Curran, Leland Chang, Mauricio J. Serrano, Ashish Ranjan, Alberto Mannari, Robert Casatuta
Publikováno v:
ISCA
The growing prevalence and computational demands of Artificial Intelligence (AI) workloads has led to widespread use of hardware accelerators in their execution. Scaling the performance of AI accelerators across generations is pivotal to their succes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::edc72fc1439c98a561b7e0104cf8a62a
https://doi.org/10.1109/isca52012.2021.00021
https://doi.org/10.1109/isca52012.2021.00021
Autor:
Xin Zhang, Vijayalakshmi Srinivasan, Wei Wang, Jungwook Choi, Siyu Koswatta, Mingu Kang, Li Yulong, Bruce M. Fleischer, Radhika Jain, Michael R. Scheuermann, Kerstin Schelm, Kailash Gopalakrishnan, Monodeep Kar, Zhibin Ren, Michael A. Guillorn, Swagath Venkataramani, Howard M. Haynie, Xiao Sun, Matthew M. Ziegler, Hung Tran, Sae Kyu Lee, Kyu-hyoun Kim, Joel Abraham Silberman, Martin Lutz, Silvia Melitta Mueller, Sunil Shukla, Pong-Fei Lu, Vidhi Zalani, Ching Zhou, Brian W. Curran, Vinay Velji Shah, Naigang Wang, Leland Chang, Robert Casatuta, Alyssa Herbert, Nianzheng Cao, Scot H. Rider, Marcel Schaal, Ankur Agrawal, Jinwook Oh, Jinwook Jung, James J. Bonanno, Matthew Cohen, Chia-Yu Chen
Publikováno v:
ISSCC
Low-precision computation is the key enabling factor to achieve high compute densities (T0PS/W and T0PS/mm2) in AI hardware accelerators across cloud and edge platforms. However, robust deep learning (DL) model accuracy equivalent to high-precision c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::531f331936a1c81912ee062cdc44a72e
https://doi.org/10.1109/isscc42613.2021.9365791
https://doi.org/10.1109/isscc42613.2021.9365791
Autor:
Gary W. Maier, Wei Wang, Siyu Koswatta, Vijayalakshmi Srinivasan, Howard M. Haynie, George D. Gristede, Bruce M. Fleischer, Michael R. Scheuermann, Matthew M. Ziegler, Sunil Shukla, Jinwook Oh, Vicktoria Ivanov, Kailash Gopalakrishnan, Martin Lutz, Ching Zhou, Xiao Sun, Silvia Melitta Mueller, Brian W. Curran, Pong-Fei Lu, Thomas W. Fox, Swagath Venkataramani, Nianzheng Cao, Ankur Agrawal, Robert Casatuta, Naigang Wang, Jungwook Choi, Vinay Velji Shah, Alex Mesh, Marcel Schaal, Scot H. Rider, Fanchieh Yee, Joel Abraham Silberman, James J. Bonanno, Michael A. Guillorn, Mingu Kang, Sae Kyu Lee, Shimon Ben-Yehuda, Erez Ophir, Chia-Yu Chen, Matthew Cohen, Yevgeny Nustov, Leland Chang, Shih-Hsien Lo
Publikováno v:
VLSI Circuits
A processor core is presented for AI training and inference products. Leading-edge compute efficiency is achieved for robust fp16 training via efficient heterogeneous 2-D systolic array-SIMD compute engines leveraging compact DLFloat16 FPUs. Architec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce688e26b703dfb25f1b3e3e01c4d0c8
https://doi.org/10.1109/vlsicircuits18222.2020.9162917
https://doi.org/10.1109/vlsicircuits18222.2020.9162917
Autor:
B. E. Aleman, M. E. Wazlowski, G. A. Van Huben, Scot H. Rider, K. D. Lamb, S. M. Rubow, Robert B. Tremaine, Warren E. Maule
Publikováno v:
IBM Journal of Research and Development. 56:3:1-3:11
IBM System i®, System p®, and System z® servers require an efficient ultrareliable high-performance memory subsystem. The fourth-generation IBM advanced memory buffer (AMB) chip provides industry-leading performance, scalability, and reliability f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::16bf6fc2cb6c7b6fd560b5cd6d325251
https://doi.org/10.1147/jrd.2011.2177897
https://doi.org/10.1147/jrd.2011.2177897