Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Sayeed A. Badrudduza"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:2524-2532
Conventional memory address decoders based on static CMOS gates incur high clock loading and unnecessary power dissipation in unselected banks. This paper presents a dynamic word line decoder which is fast, has reduced active and leakage power dissip
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ddd5eca8a151b0818b2cf0e641626bf
https://doi.org/10.1109/jssc.2008.2005813
https://doi.org/10.1109/jssc.2008.2005813
Publikováno v:
Journal of Low Power Electronics. 2:412-424
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ab4e486e54723aac4e6be4535103e55d
https://doi.org/10.1166/jolpe.2006.102
https://doi.org/10.1166/jolpe.2006.102
Autor:
J. Pape, Nam-Sung Kim, Martin Ostermayr, Deleep R. Nair, Melanie J. Sherony, Craig S. Lage, Jaeger Daniel, Franck Arnaud, Y. Gao, Deok-Hyung Lee, H.S. Yang, C. Schiller, X. Chen, S. Stiffler, An L. Steegen, Kenneth J. Stein, J. Sudijono, Christopher V. Baiocco, Haoren Zhuang, Robert C. Wong, Y. Takasu, Ho-Kyu Kang, Sayeed A. Badrudduza, J. Wallner, Laegu Kang, James Chingwei Li, Aaron Thean, Y.W. Teh, L. Zhuang, R. Hasumi, S. Samavedam, D.P. Sun, Mukesh Khare
Publikováno v:
2008 IEEE International Electron Devices Meeting.
This paper describes SRAM scaling for 32 nm low power bulk technology, enabled by high-K metal gate process, down to 0.149 mum2 and 0.124 mum2. SRAM access stability and write margin are significantly improved through a 50% Vt mismatch reduction, tha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bcc347a597544ead57bce41996b65ef0
https://doi.org/10.1109/iedm.2008.4796660
https://doi.org/10.1109/iedm.2008.4796660
Publikováno v:
Journal of Computers. 3
Semiconductor manufacturing process scaling increases leakage and transistor variations, both of which are problematic for static random access memory (SRAM). Since SRAM is a critical component in modern CMOS integrated circuits, novel approaches to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::948b2f33c76683416015d1b64aae2109
https://doi.org/10.4304/jcp.3.4.39-49
https://doi.org/10.4304/jcp.3.4.39-49
Publikováno v:
VLSI Design
Highly scaled processes increase leakage and transistor variations, both of which are problematic for SRAM, which is pervasive in modern CMOS integrated circuits. Here, a six transistor SRAM cell is presented that does not suffer from reduced stabili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f09fd10ed6fbae6a2f99d81617918d2
https://doi.org/10.1109/vlsid.2007.96
https://doi.org/10.1109/vlsid.2007.96