Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Savithri Sundareswaran"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27:864-874
A slew-driven clock tree synthesis (SLECTS) methodology is proposed for nanoscale technologies where the interconnect resistance dominates device resistance, thereby increasing the challenge of satisfying the slew constraint. This issue is exacerbate
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e26c04557d5a137a45c0033259026211
https://doi.org/10.1109/tvlsi.2018.2888958
https://doi.org/10.1109/tvlsi.2018.2888958
Power gating is a widely used leakage power saving strategy in modern chip designs. However, power gating introduces unique power integrity issues and trade-offs between switching and rush current (wake-up) supply noises. At the same time, the amount
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2847647a0cc76e0c9b7182df35f8619a
https://escholarship.org/uc/item/627706j4
https://escholarship.org/uc/item/627706j4
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25:144-154
Power-distribution networks of very large-scale integrated (VLSI) chips should be designed carefully to ensure reliable performance. A sound power network requires an adequate number of power-supply input connections (pads and pins). Placing them at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22adced4508c26f8bba6a69cc7b79575
https://doi.org/10.1109/tcad.2005.852459
https://doi.org/10.1109/tcad.2005.852459
Publikováno v:
IEEE Design & Test of Computers. 20:16-22
Although it is tempting to think of the power grid as an independent medium of the transfer of energy from the package to the devices in the IC, some second-order technology-related effects can sometimes cause unforeseen problems. This article focuse
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b10b70492a6baca7c603732d22f58a7f
https://doi.org/10.1109/mdt.2003.1198681
https://doi.org/10.1109/mdt.2003.1198681
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21:1180-1195
Static timing analysis has traditionally used the PERT method for identifying the critical path of a circuit. The authors show in this paper that due to the influence of the transition time of a signal on the subsequent path delay, the traditional ti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8226278f1670cdc98c4b7d44048f9d62
https://doi.org/10.1109/tcad.2002.802274
https://doi.org/10.1109/tcad.2002.802274
Autor:
Puneet Sharma, Savithri Sundareswaran, Venkat Kolagunta, Brad Smith, Surya Veeraraghavan, Matthew A. Thompson, Donald Hall
Publikováno v:
2012 IEEE International Conference on Microelectronic Test Structures.
Library elements (or standard cells) are basic building blocks of integrated circuits. These are built early in the technology cycle. Small changes to library elements can result in significant power/performance changes to large designs instantiating
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ba17dddd13fd66dd310611cd5e89a27f
https://doi.org/10.1109/icmts.2012.6190603
https://doi.org/10.1109/icmts.2012.6190603
Autor:
Robert L. Maziasz, Vladimir P. Rozenfeld, Mukhanov Konstantin, Mikhail Anatolievich Sotnikov, Savithri Sundareswaran
Publikováno v:
ISQED
Standard cells are basic building blocks, crucial for digital designs. Manufacturability improvements in standard cells have huge leverage, returning big benefits in yield and performance to all designs which may use them. Most of the benefits can be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3efc075f19c6a0b9872e3ffd78c40a29
https://doi.org/10.1109/isqed.2011.5770762
https://doi.org/10.1109/isqed.2011.5770762
Publikováno v:
ISPD
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. How to design robust cells under variations plays a crucial role in the o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8e36689ba59de988059af03a87445fec
https://doi.org/10.1145/1735023.1735053
https://doi.org/10.1145/1735023.1735053
Publikováno v:
SPIE Proceedings.
As the transistors are scaled down, undesirable performance mismatch in identically designed transistors increases and hence causes greater impact on circuit performance and yield. Since Line-End Roughness (LER) has been reported to be in the order o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::567822ec6529b40c623e946338008136
https://doi.org/10.1117/12.814355
https://doi.org/10.1117/12.814355
Publikováno v:
ISQED
For timing analysis, each flip-flop and latch in a standard library is characterized for two constraints: setup time and hold time constraints. These constraints need to be characterized for their sensitivities to the variation parameters in order to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::53d84aea761b86d9989232f31f0424cb
https://doi.org/10.1109/isqed.2009.4810272
https://doi.org/10.1109/isqed.2009.4810272