Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Saurabh K. Tiwary"'
Publikováno v:
ICCAD
Boolean satisfiability (SAT) based methods have traditionally been popular for formally verifying properties for digital circuits. We present a novel methodology for formulating a SPICE-type circuit simulation problem as a satisfiability problem. We
Publikováno v:
VLSI Design
Scaling with Moore’s law is taking us to feature sizes of 32nm and smaller. At these technology nodes designers are faced with an explosion in design complexity at all levels. In this tutorial we discuss three somewhat novel and particularly confou
Autor:
Rob A. Rutenbar, Saurabh K. Tiwary
Publikováno v:
CICC
Trajectory methods offer an attractive methodology for automated extraction of macromodels from a set of training simulations. A pervasive concern with models based on regression is the lack of certainty about where they fit correctly. The authors sh
Publikováno v:
DAC
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front effi
Autor:
Rob A. Rutenbar, Saurabh K. Tiwary
Publikováno v:
ICCAD
Trajectory-based methods offer an attractive methodology for automated, on-demand generation of macro-models for custom circuits. These models are generated by sampling the state trajectory of a circuit as it simulates in the time domain, and buildin
Autor:
Rob A. Rutenbar, Saurabh K. Tiwary
Publikováno v:
DAC
Trajectory methods sample the state trajectory of a circuit as it simulates in the time domain, and build macromodels by reducing and interpolating among the linearizations created at a suitably spaced subset of the time points visited during trainin