Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Satish kumar Das"'
Autor:
Kishore Chandra Singh, Sudhansu Mohan Biswal, Biswajit Baral, Satish Kumar Das, Prasantakumar Khuntia
Publikováno v:
2022 IEEE International Conference of Electron Devices Society Kolkata Chapter (EDKCON).
Autor:
Lalat Indu Giri, Satish Kumar Das, Umakanta Nanda, Sudhansu Mohan Biswal, Chandan Kumar Pandey
Publikováno v:
Silicon. 14:2965-2973
Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus e
Publikováno v:
2021 19th OITS International Conference on Information Technology (OCIT).
Publikováno v:
Silicon. 12:1567-1574
In this paper a double gate MOSFET having non uniform channel doping with gate stack structure is explored to study the linearity analysis. The extractions of linearity parameters confirm the novelty of the device and also enable us to achieve better
Publikováno v:
ECS Journal of Solid State Science and Technology. 10:073001
Publikováno v:
ICICCT 2019 – System Reliability, Quality Control, Safety, Maintenance and Management ISBN: 9789811384608
In the work purposed, the behavior of JLTMCSG MOSFET has been investigated by incorporating Dual Metals and Single Metal Gate with respect to different device parameters. The conclusion derived from the investigation reveals that DIBL can be suppress
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::35d5d69e1eb7c9bfba3cd41bdfa0d8d4
https://doi.org/10.1007/978-981-13-8461-5_92
https://doi.org/10.1007/978-981-13-8461-5_92
Autor:
Debasish Nayak, Satish Kumar Das, Sudhansu Mohan Biswal, Dhananjaya Tripathy, Biswajit Baral, Umakanta Nanda, Sanjit Kumar Swain
Publikováno v:
2019 Devices for Integrated Circuit (DevIC).
In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect to different spacer variations in order to reduce the short channel effect challenges and simultaneously increasing the device performance. Silicon is u
Performance Analysis of Staggered Heterojunction based SRG TFET biosensor for health IoT application
Autor:
Debasish Nayak, Satish Kumar Das, Biswajit Baral, Sanjit Kumar Swain, Sudhansu Mohan Biswal, Dhananja Tripthy, Umakanta Nanda
Publikováno v:
2019 Devices for Integrated Circuit (DevIC).
This paper presents the performance of SRG Tunnel FET biosensor. Here the different device parameters are deliberate to meet the requirement of the technological development. Focus is made on how TFET can be a substitute ahead of CMOS characteristics
Autor:
Sudhansu Mohan Biswal, Biswajit Baral, Dhananjaya Tripthy, Prakash Kumar Rout, Umakanta Nanda, Sanjit Kumar Swain, Debasish Nayak, Satish Kumar Das
Publikováno v:
2019 Devices for Integrated Circuit (DevIC).
The modern electronics gadget has influenced tremendously every aspects of life. The demand to add more and more functionality has forced to increase the performance of the processor. To ensure a robust data supply to the processor a high performance
Autor:
Biswajit Baral, Sarosij Adak, Sudhansu Mohan Biswal, Dhananjaya Tripathy, Debasish Navak, Sanjit Kumar Swain, Umakanta Nanda, Asmit Amlan Sahoo, Satish Kumar Das
Publikováno v:
2019 Devices for Integrated Circuit (DevIC).
This paper presents the performance of non-uniformed doped double gate (DG) MOSFET with different spacer variations with an aim to analysis the effects of short channel and various performance metrics. In this work we have taken silicon as the channe