Zobrazeno 1 - 10
of 59
pro vyhledávání: '"Sascha Uhrig"'
Publikováno v:
Security and Communication Networks, Vol 2019 (2019)
This book constitutes the proceedings of the 32nd International Conference on Architecture of Computing Systems, ARCS 2019, held in Copenhagen, Denmark, in May 2019. The 24 full papers presented in this volume were carefully reviewed and selected fro
Autor:
Johannes Freitag, Sascha Uhrig
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783319776095
ARCS
ARCS
In critical and hard real-time applications multicore processors are still not used very often. One of the reasons is the lack of timing predictability or the high Worst Case Execution Time (WCET) overestimation caused by the use of shared resources.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::78eb14f27c4ce6c3c6d5259055a191a6
https://doi.org/10.1007/978-3-319-77610-1_4
https://doi.org/10.1007/978-3-319-77610-1_4
Autor:
Johannes Freitag, Marco Caccamo, Giorgio Buttazzo, Sascha Uhrig, Renato Mancuso, Alessandra Melani
Publikováno v:
RTCSA
Although multicore chips are quickly replacing uniprocessor ones, safety-critical embedded systems are still developed using single processor architecture. The reasons mainly concern predictability and certification issues. This paper proposes a sche
Publikováno v:
Concurrency and Computation: Practice and Experience. 26:1342-1354
In multicore systems, the concurrent access to shared data generates a bottleneck for the system performance. Cache coherence techniques have been introduced to enable fast access while preserving the data coherence, but these coherence protocols are
Autor:
Eduardo Quinones, Stefan Metzlaff, Theo Ungerer, Jörg Mische, Mike Gerdes, Marco Paolieri, Sascha Uhrig, Francisco J. Cazorla
Publikováno v:
ACM Transactions on Embedded Computing Systems
Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case exec
Autor:
Xing Cai, Norbert Druml, Erwin Schoitsch, Daniel Schneider, Juha Kuusela, Rolf Ernst, Peter Tummeltshammer, Sergio Saez, Juan Carlos Perez-Cortes, Sascha Uhrig, Jan van Deventer, Egon Wuchner, Alfred Hoess, Haris Isakovic, Thierry Goubier, Geir Yngve Paulsen, Massimo Traversone, Bjorn Nordmoen, Michael Geissel, Eric Armengaud, Adam Kostrzewa, Hans Petter Dahle, Jürgen Salecker, Philippe Dore, Marinus Johannes Adrianus Maria Van Helvoort, Thomas Soderqvist, Werner Weber, Frank Oppenheimer
Publikováno v:
DSD
Since April 2014 the Artemis/ECSEL project EMC2 is running and provides significant results. EMC2 stands for "Embedded Multi-Core Systems for Mixed Criticality Applications in Dynamic and Changeable Real-Time Environments". In this paper we report re
Publikováno v:
RTAS
In this work, we present an initial step towards enabling TT scheduling on a real COTS multicore platform P4080. It takes into account inter-core interferences in the on-chip network and the memory sub-system. We propose an approach comprising a runt
Autor:
Jörg Mische, Hugues Cassé, Florian Kluge, Sebastian Kehr, Sascha Uhrig, Francisco J. Cazorla, Armelle Bonenfant, Bert Böddeker, Lucie Matusova, Jaume Abella, Christian Bradatsch, Milos Panic, Zai Jian Jia Li, Mike Gerdes, Theo Ungerer, Carles Hernandez, Christine Rochange, Martin Frieb, Eduardo Quinones, David George, Zlatko Petrov, Ian Broster, Pavel Zaykov, Ralf Jahr, Hans Regler, Pascal Sainrat, Arthur Pyka, Haluk Ozaktas, Andreas Hugl, Alexander Stegmeier, Nick Lay, Mathias Rohde
Publikováno v:
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS), ACM, 2016, 15 (3), ⟨10.1145/2910589⟩
ACM Transactions on Embedded Computing Systems (TECS), ACM, 2016, 15 (3), ⟨10.1145/2910589⟩
International audience; The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eba8fcccc1a4e0b12f79e039b2c091a7
https://opus.bibliothek.uni-augsburg.de/opus4/frontdoor/index/index/docId/54088
https://opus.bibliothek.uni-augsburg.de/opus4/frontdoor/index/index/docId/54088
Autor:
Sascha Uhrig
Publikováno v:
PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware. 28:157-160