Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Sarita Uniyal"'
Publikováno v:
2022 IEEE 7th International conference for Convergence in Technology (I2CT).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2beb32ace2d25127f30536a13e10bdd
https://doi.org/10.1109/i2ct54291.2022.9824947
https://doi.org/10.1109/i2ct54291.2022.9824947
Publikováno v:
2021 2nd Global Conference for Advancement in Technology (GCAT).
The schematic of class-AB yield stage with BJT, CMOS, BiCMOS is carried out in cadence virtuoso simulator. Every transistor size in the operational amp is designed, validated and BiCMOS operated at supply voltage of 3.3V. The proposed amplifier circu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8860aa2f0ba6aed39581639db0ad9785
https://doi.org/10.1109/gcat52182.2021.9587801
https://doi.org/10.1109/gcat52182.2021.9587801
Publikováno v:
2015 International Conference on Signal Processing, Computing and Control (ISPCC).
This paper presents a 4×4 Bit Multiplier using two phase clocked adiabatic static CMOS logic (2PASCL) along with introduction of sleep mode transistor. Modified Adiabatic Multiplier and modified EXOR logic have been implemented on Tanner EDA tool us
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8db53c4d362fb52626c1732d4c93f948
https://doi.org/10.1109/ispcc.2015.7375037
https://doi.org/10.1109/ispcc.2015.7375037
Autor:
Pittala, Suresh Kumar, Rani, A. Jhansi
Publikováno v:
Annals of the University Dunarea de Jos of Galati Fascicle III: Electrotechnics, Electronics, Automatic Control & Informatics; 2017, Vol. 40 Issue 1, p23-28, 6p
Publikováno v:
2015 International Conference on Signal Processing, Computing & Control (ISPCC); 2015, p262-265, 4p
Publikováno v:
2015 International Conference on Signal Processing, Computing & Control (ISPCC); 2015, pxxviii-xxxiii, 6p
Publikováno v:
2015 International Conference on Signal Processing, Computing & Control (ISPCC); 2015, pxiii-xxiv, 12p