Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Sarasvathi Thangaraju"'
Autor:
Mark Scholefield, Dingyou Zhang, Tong Qing Chen, Sarasvathi Thangaraju, Wonwoo Kim, Ming Lei, Christian Klewer, Kumarapuram Gopalakrishnan, Daniel Smith, Abhishek Vikram, Himani Kamineni, Victor Lim, Ramakanth Alapati
Publikováno v:
Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2014:001506-001522
This paper reports on a new type of through-silicon via (TSV) defect, silicon fin defect, which was found after TSV deep-reactive-ion-etching (DRIE) process for TSV integration with front-end-of-line (FEOL) devices. One possible root cause for this d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3476245113154b36ceb2b3146c91c946
https://doi.org/10.4071/2014dpc-wp14
https://doi.org/10.4071/2014dpc-wp14
Autor:
Yuichi Miyamori, Yann Civale, Dimitrios Velenis, Annemie Van Ammel, Vladimir Cherman, A. Cockburn, Youssef Travaly, Bart Swinnen, Zsolt Tkei, Virginie Gravey, Sarasvathi Thangaraju, Nirajan Kumar, Geert Van der Plas, Zhitao Cao, Augusto Redolfi, Eric Beyne, Kristof Croes
Publikováno v:
Microelectronic Engineering. 106:155-159
Barrier reliability in 3D through-Si via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::68c10e404cc61dba55d0bfab169cc66a
https://doi.org/10.1016/j.mee.2013.01.019
https://doi.org/10.1016/j.mee.2013.01.019
Autor:
Dingyou Zhang, Mark Scholefield, Christian Klewer, Wonwoo Kim, Ramakanth Alapati, Abhishek Vikram, Himani Kamineni, Ming Lei, Daniel Smith, Sarasvathi Thangaraju, Victor Lim
Publikováno v:
Electronics Letters. 50:954-956
A new type of through-silicon via (TSV) defect, silicon fin defect, which was found after the TSV deep-reactive-ion-etching process at the TSV bottom is reported. These defects are considered killer TSV defects that may cause process or mechanical fa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2209ce57a316b12d98feffb442d83b4c
https://doi.org/10.1049/el.2014.0974
https://doi.org/10.1049/el.2014.0974
Autor:
C. Wang, Shinichiro Kakita, Rudy Ratnadurai Giridharan, Dingyou Zhang, Luke England, A. Selsley, S. Baral, Sarasvathi Thangaraju, G. Kumarapuram, Mohamed A. Rabie, Wonwoo Kim, R. McGowan, Holly Edmundson, Gu Sipeng, Vijayalakshmi Seshachalam
Publikováno v:
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).
This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, Through Silicon Vias (TSV), of 3μm top entrant critical dimension (CD) and 50μm depth. Higher AR TSV integration is explored due to the lower stress
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d38844234b0657299f27a187e4d85b9
https://doi.org/10.1109/asmc.2014.6846976
https://doi.org/10.1109/asmc.2014.6846976
Autor:
Dingyou Zhang, Hemant Amin, Sarasvathi Thangaraju, Himani Kamineni, Ramakanth Alapati, Alok Vaid, Jonathan Peak, Wonwoo Kim, Nigel Smith, Timothy Norman Johnson, Brennan Peterson, Ke Xiao, Yeong-Uk Ko, Holly Edmundson, Padraig Timoney, Daniel Smith, Daniel Fisher
Publikováno v:
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).
High aspect ratio through silicon vias (TSV) present a challenge for measurement of bottom critical dimension (BCD) and depth. TSVs smaller than 5 micron diameter with greater than 12:1 depth to BCD aspect ratio have particularly poor signal to noise
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b77d25fc1b78b571329aa3c8813595b1
https://doi.org/10.1109/asmc.2014.6846973
https://doi.org/10.1109/asmc.2014.6846973
Autor:
Mahadevan Iyer Natarajan, Sing Fui Yap, Daniel Smith, Rakesh Ranjan, Francis Benistant, C.S. Premachandran, Mohamed A. Rabie, Ramakanth Alapati, Sarasvathi Thangaraju
Publikováno v:
IEEE International Interconnect Technology Conference.
For the first time, a near-Zero Keep Out Zone TSV capability is demonstrated utilizing the Middle Of Line (MoL) layer stack process development and optimization. This is MoL layer stack consisted of a nitride, PMD oxide, and contact protection layer.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::587fd356d0d5c10a5ee9386b964ed778
https://doi.org/10.1109/iitc.2014.6831870
https://doi.org/10.1109/iitc.2014.6831870
Autor:
Himani Kamineni, Dingyou Zhang, Daniel Smith, Sukeshwar Kannan, Shan Gao, Ramakanth Alapati, Sarasvathi Thangaraju
Publikováno v:
IEEE International Interconnect Technology Conference.
This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The character
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c2c8fc566b763d31fc4780a9c1527ca
https://doi.org/10.1109/iitc.2014.6831869
https://doi.org/10.1109/iitc.2014.6831869
Autor:
Daniel Smith, Daniel Fisher, Sung Pyo Jung, Jonathan Peak, Alok Vaid, Wonwoo Kim, Timothy Norman Johnson, Padraig Timoney, Ramakanth Alapati, Hemant Amin, Sarasvathi Thangaraju, Yeong-Uk Ko
Publikováno v:
25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).
White light interferometry (WLI) has been used in the semiconductor industry for the measurement of topography, step height, and via depth, utilizing its fundamentally short coherence length. This allows the tool to achieve nanometer level resolution
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c75d4ed6a89e7491473bcf6422dae001
https://doi.org/10.1109/asmc.2014.6847019
https://doi.org/10.1109/asmc.2014.6847019
Autor:
Augusto Redolfi, Sarasvathi Thangaraju, Geert Van der Plas, Virginie Gravey, Dimitrios Velenis, Yann Civale, Nirajan Kumar, Youssef Travaly, Philippe Soussan, Kristof Croes, Vladimir Cherman, Annemie Van Ammel, A. Cockburn, Yuichi Miyamori, Bart Swinnen, Deniz Sabuncuoglu Tezcan, Paul Hendrickx, Eric Beyne, Zsolt Tokei, Zhitao Cao
Publikováno v:
2011 IEEE International Interconnect Technology Conference.
Barrier reliability in 3D Through-Si Via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::440d19d1ee3dfe40f31be44b8f352f54
https://doi.org/10.1109/iitc.2011.5940352
https://doi.org/10.1109/iitc.2011.5940352
Autor:
Sarasvathi Thangaraju, Kevin Vandersmissen, Youssef Travaly, E. Van Besien, Harold Dekkers, Alex Radisic, Nancy Heylen, Eric Beyne, M. Kostermans, Bart Swinnen, Simon Rodet, Patrick Jaenen, P. Nolmans, Augusto Redolfi, A. Van Ammel, Dimitrios Velenis, Thomas Witters, N. Jourdan, U. Baier, Harold Philipsen
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
The establishment of a cost-effective Through Silicon Vias (TSV) fabrication process integrated to a CMOS flow with industrially available tools is of high interest for the electronics industry because such process can produce more compact systems. W
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76533ad37fc04896c5493692b8832153
https://doi.org/10.1109/ectc.2011.5898692
https://doi.org/10.1109/ectc.2011.5898692