Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Saptarsi Das"'
Publikováno v:
ISCAS
As throughput of neural network accelerator datapaths have grown, memory has consistently fallen behind. Although attempts have been made to improve performance of neural networks via approaches such as batching, several layers often starve for memor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c36c0f05674b394206f447dc33cbaf0
https://doi.org/10.1109/iscas51556.2021.9401315
https://doi.org/10.1109/iscas51556.2021.9401315
Publikováno v:
ISCAS
Modern Artificial Intelligence (AI) systems deploy Convolution Neural Networks (CNN) as they offer very high accuracy. Computational complexity of CNNs necessitates hardware acceleration, especially in mobile phones and other hand held devices due to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::686033a4597bafc4bb874a660eeba2e4
https://doi.org/10.1109/iscas45731.2020.9180403
https://doi.org/10.1109/iscas45731.2020.9180403
Publikováno v:
Integration. 58:320-328
Transistor supply voltages no longer scales at the same rate as transistor density and frequency of operation. This has led to the Dark Silicon problem, wherein only a fraction of transistors can operate at maximum frequency and nominal voltage, in o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1babb19555aaa3cd023209fc1481ba53
https://doi.org/10.1016/j.vlsi.2017.02.009
https://doi.org/10.1016/j.vlsi.2017.02.009
Autor:
Santhi Natarajan, S. K. Nandy, Farhad Merchant, Adithya Pulli, Kavitha T. Madhu, Saptarsi Das, Madhav Krishna, Ipsita Biswas, Nalesh Sivanandan, Ranjani Narayan
Publikováno v:
Journal of Systems Architecture. 60:592-614
In this paper we present a framework for realizing arbitrary instruction set extensions (IE) that are identified post-silicon. The proposed framework has two components viz., an IE synthesis methodology and the architecture of a reconfigurable data-p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1eff6999875bca27c975709f8f39198a
https://doi.org/10.1016/j.sysarc.2014.06.002
https://doi.org/10.1016/j.sysarc.2014.06.002
Publikováno v:
PARMA-DITAM@HiPEAC
Performance of an application on a many-core machine primarily hinges on the ability of the architecture to exploit parallelism and to provide fast memory accesses. Exploiting parallelism in static application graphs on a multicore target is relative
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e3ea1970f90378d41aa5257ce5bafe9
https://doi.org/10.1145/2872421.2872426
https://doi.org/10.1145/2872421.2872426
Publikováno v:
VLSI Design
In this paper, we present an architecture named REDEFINE Hyper Cell Multicore (RHyMe) designed to efficiently realize HPC application kernels, such as loops. RHyMe relies on the compiler to generate the meta-data for its functioning. Most of the orch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::72d1b12d726aecf04574cb9e5491e6fa
https://doi.org/10.1109/vlsid.2016.29
https://doi.org/10.1109/vlsid.2016.29
Autor:
Siba Prasad Dash, Saptarsi Das, S. K. Nandy, Ranjani Narayan, Maheshkumar P Jagtap, Chandan Haldar, Ganesh Garga
Publikováno v:
Defence Science Journal. 62:25-31
The highest levels of security can be achieved through the use of more than one type of cryptographic algorithm for each security function. In this paper, the REDEFINE polymorphic architecture is presented as an architecture framework that can optima
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70485c82db35ba454d625a9b4d3905b2
https://doi.org/10.14429/dsj.62.1438
https://doi.org/10.14429/dsj.62.1438
Publikováno v:
iNIS
With transistor energy efficiency not scaling at the same rate as transistor density and frequency, CMOS technology has hit a utilization wall, whereby large portions of the chip remain under clocked. To improve performance, while keeping power dissi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f07f7835a9e7cf52c6cd64c39409684f
https://doi.org/10.1109/inis.2015.39
https://doi.org/10.1109/inis.2015.39
Autor:
Masahiro Fujita, Ratna Krishnamoorthy, S. K. Nandy, Keshavan Varadarajan, Saptarsi Das, Mythri Alle, Ranjani Narayan
Publikováno v:
IPSJ Transactions on System LSI Design Methodology. 4:193-209
Coarse Grain Reconfigurable Architectures (CGRA) support spatial and temporal computation to speedup execution and reduce reconfiguration time. Thus compilation involves partitioning instructions spatially and scheduling them temporally. The task of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0cafbb232481034aebd1f5df8ffe79b
https://doi.org/10.2197/ipsjtsldm.4.193
https://doi.org/10.2197/ipsjtsldm.4.193
Autor:
S. K. Nandy, Prasenjit Biswas, Keshavan Varadarajan, Ranjani Narayan, Adarsh Rao, Saptarsi Das, Mythri Alle, Jugantor Chetia, Nimmy Joseph, C. Ramesh Reddy, Alexander Fell
Publikováno v:
ACM Transactions on Embedded Computing Systems. 9:1-48
Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically intero
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4724d68e774a3d8a3ecdde144d6c101b
https://doi.org/10.1145/1596543.1596545
https://doi.org/10.1145/1596543.1596545