Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Sanku Mukherjee"'
Autor:
Manish Jain, C. Huang, Keisuke Saito, Wendemagegnehu T. Beyene, Kun-Yung Ken Chang, J. Wei, Deborah Dressier, T. J. Chin, Catherine Chen, Dave Secker, Phuong Le, Vijay Gadde, Chris Madden, Xingchao Yuan, Ting Wu, Chanh Tran, Mahabaleshwara, Sanku Mukherjee, Navin Kumar Mishra, Ling Yang, Leneesh Raghavan, Arul Sendhil, Amir Amirkhany, Hai Lan, Arun Vaidyanath, R. Schmitt, Gundlapalli Shanmukha Srinivas, Shuaeb Fazeel, Mohammad Hekmat, Kambiz Kaviani, Kapil Vyas, Jie Shen
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:911-925
This paper presents a tri-modal asymmetric memory controller interface that achieves 12.8-Gbps single-ended (SE) signaling over 3" stripline FR4 traces. The controller can be configured to communicate with commercially available GDDR5 and DDR3 memori
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::421978d9bf7442239b44035690fb198d
https://doi.org/10.1109/jssc.2012.2185369
https://doi.org/10.1109/jssc.2012.2185369
Publikováno v:
VLSI Design
Single-ended memory interfaces have gone through a remarkable increase in data rates over the last decade increasing the challenges faced by system designers and OEMs. One of the major challenges in single-ended system design is optimizing the refere
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d588f3245f44ffb7266eee496c334f0f
https://doi.org/10.1109/vlsid.2013.204
https://doi.org/10.1109/vlsid.2013.204
Publikováno v:
VLSI Design
Resetting flip flops in high speed clock domain across wide silicon area is a challenge due to significant delay variations between the clock and reset signals. In this paper, a novel method of transmitting Reset Through the Clock (RTC) tree is propo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9323730e2888a23f4c39e515353c48fc
https://doi.org/10.1109/vlsid.2013.166
https://doi.org/10.1109/vlsid.2013.166
Publikováno v:
2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.
While the need for higher graphics memory bandwidth continues to grow, it is evident that owing to the multitude of challenges in single ended signaling, pushing data rates beyond 6 Gbps is exceedingly difficult. To isolate, quantify and combat the m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66d34cdb6be44fca04f92989e7ee2269
https://doi.org/10.1109/epeps.2012.6457838
https://doi.org/10.1109/epeps.2012.6457838
Autor:
Wendemagegnehu T. Beyene, Ling Yang, Amir Amirkhany, Dave Secker, R. Schmitt, Hai Lan, Sanku Mukherjee, Chris Madden, Kambiz Kaviani
Publikováno v:
2011 IEEE 20th Conference on Electrical Performance of Electronic Packaging and Systems.
The design of a high-speed single-ended parallel interface using conventional package and board technologies is presented. The system uses asymmetrical architecture where the equalization and timing adjustment circuits for both memory WRITE and READ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::69c211f6554c4f1194a7a39c8fe1e2fb
https://doi.org/10.1109/epeps.2011.6100208
https://doi.org/10.1109/epeps.2011.6100208
Publikováno v:
CICC
A bi-modal x32 memory interface supports 6.4-Gbps GDDR5 signaling as well as 2.4-Gbps DDR3 signaling with a 1.5V IO supply. The interface incorporates a novel driver and pre-driver structure that supports one-tap equalization and presents very small
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8932f86f0d7be9967632f0f87ffde82
https://doi.org/10.1109/cicc.2011.6055399
https://doi.org/10.1109/cicc.2011.6055399