Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Sankatali Venkateswarlu"'
Autor:
Sankatali Venkateswarlu, Subrat Mishra, Herman Oprins, Bjorn Vermeersch, Moritz Brunion, Jun-Han Han, Mircea R. Stan, Pieter Weckx, Francky Catthoor
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 30:1668-1676
Publikováno v:
IEEE Transactions on Electron Devices. 68:4723-4728
In this article, we investigate the electro-thermal (ET) performance of stacked Si gate-all-around (GAA) nanosheet FET (NSHFET) by adopting the metal (M0) source/drain (S/D) engineered contacts such as M0-wrap around the Si S/D epitaxial regions and
Autor:
Sankatali Venkateswarlu, Kaushik Nayak
Publikováno v:
IEEE Transactions on Electron Devices. 67:4493-4499
This article reports that Hetero-interfacial-thermal resistance (HITR) due to phonon scattering and weak electron–phonon coupling at hetero-interfaces, can impact stacked Si gate-all-around (GAA) nanosheet field effect transistor (NSHFET) self-heat
Publikováno v:
IEEE Transactions on Electron Devices. 66:4646-4652
We report the numerical simulation study on the characteristic variability of 10-nm SOI Multi Fin n-FET due to the impact of random fluctuation sources such as gate work function variability induced by metal gate granularity (MGG) and Fin line edge r
Publikováno v:
2020 5th IEEE International Conference on Emerging Electronics (ICEE).
Autor:
Sankatali Venkateswarlu, Kaushik Nayak
Publikováno v:
2020 5th IEEE International Conference on Emerging Electronics (ICEE).
Publikováno v:
2020 4th IEEE Electron Devices Technology & Manufacturing Conference (EDTM).
In this paper, work function variability (WFV) of stacked nanosheet FET (NSHFET) has been numerically investigated using 3-D quantum corrected Drift-Diffusion simulation framework for sub-7nm high performance logic applications. The WFV induced NSHFE
Publikováno v:
IEEE Transactions on Electron Devices. 65:2721-2728
Device self-heating effects (SHEs) in nonplanar Si MOS transistors such as fin field-effect transistors (FinFETs) and nanowire FETs have become a serious issue in designing well-tempered CMOS devices for future logic nodes. The device thermal contact