Zobrazeno 1 - 10
of 78
pro vyhledávání: '"Sanjay Natarajan"'
Publikováno v:
Proceeding of Flexible Automation and Integrated Manufacturing 1998.
Publikováno v:
Proceeding of Flexible Automation and Integrated Manufacturing 1998.
Autor:
Sanjay Natarajan
Publikováno v:
Proceeding of Flexible Automation and Integrated Manufacturing 1998.
Publikováno v:
INTERNATIONAL JOURNAL OF SCIENTIFIC RESEARCH. :1-3
Introduction Both High Ligation/ Stripping and Radiofrequency ablation have been accepted as a standard in the management of varicose veins and are being performed by general and vascular surgeons. Objectives To compare the postoperative outcome in t
Publikováno v:
Rapid Prototyping Journal. 26:238-248
Purpose Extrusion-based additive manufacturing (AM) has been considered as a promising technique to fabricate scaffolds for tissue engineering due to affordability, versatility and ability to print porous structures. The reliability and controllabili
Autor:
Jaehyun Lee, El Mehdi Bazizi, Victor Moroz, Sanjay Natarajan, Xi-Wei Lin, Buvna Ayyagari-Sangmalli, Benjamin Colombeau, Ashish Pal, Blessy Alexander, Plamen Asenov
Publikováno v:
Design-Process-Technology Co-optimization XV.
In this paper, we describe a framework to enable the memory array simulations for Materials to Systems CooptimizationTM (MSCOTM) flows. The methodology is applied for projected 3 nm logic FinFET technology node SRAM array. To form the SRAM array, a
Autor:
M. Cogorno, S. C. Kung, Tushar Mandrekar, Balasubramanian S. Pranatharthi Haran, Mary Breton, Hemanth Jagannathan, Jingyun Zhang, James Chingwei Li, Benjamin Colombeau, Huimei Zhou, Shogo Mochizuki, Koji Watanabe, Nicolas Loubet, Sanjay Natarajan, M. Stolfi, P. Chen
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
In this paper, horizontal gate-all-around (hGAA) devices with a SiGe cladded nanosheet (NS) channel have been explored for their potential benefits of Vt modulation and improved NBTI. The SiGe cladded NS channel was formed through trimming of the Si
Materials Technology Co-Optimization of Self-Aligned Gate Contact for Advanced CMOS Technology Nodes
Autor:
Keyvan Kashefizadeh, Nancy Fung, T. E. Sato, Nitin K. Ingle, W. Xu, W. Lei, Benjamin Colombeau, Anchuan Wang, Yu Lei, Ajay Bhatnagar, Ashish Pal, P. Wang, Sanjay Natarajan, D. Cui, Angada B. Sachid, Avgerinos V. Gelatos, Blessy Alexander, C. Lee, B. Brown, D. Hwang, Sean M. Seutter, K. Mikhaylichenko, T. H. Ha, M. Kawasaki, Yi Xu, Buvna Ayyagari, J. Ferrell, M. Cogorno, El Mehdi Bazizi, T. Luu
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible ma
Autor:
Gaurav Thareja, El Mehdi Bazizi, Samuel Lin, Ashish Pal, Mehdi Saremi, Sushant Mittal, Blessy Alexander, Benjamin Colombeau, Sanjay Natarajan, Angada B. Sachid, Buvna Ayyagari
Publikováno v:
2019 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
Impact of air-spacer at MOL and BEOL on circuit performance at 3nm technology node is studied. Our modeling results show that by introducing air-spacer at MOL and BEOL, parasitic capacitance can be reduced by 18% and circuit performance as simulated
Autor:
X-W. Lin, Victor Moroz, Jacky Huang, B. Cheng, Chidi Chidambaram, Munkang Choi, D. Sherlekar, S. C. Song, P. Asenov, Sanjay Natarajan, Matthias Bauer, Benjamin Colombeau
Publikováno v:
2019 Symposium on VLSI Technology.
We explore four different technology and design options for transistors and library cells for a low power supply voltage of 0.4 V and circuit statistics representative of artificial intelligence (AI) applications. The design rules correspond to 2nm n