Výsledky vyhledávání - "Sanjay Dabral"

A 2.488–11.2 Gb/s SerDes in 40 nm low-leakage CMOS with multi-protocol compatibility for FPGA applications

Autor: Alvin Wang, Khaldoon Abugharbieh, Claude R. Gauthier, Bendik Kleveland, Shaishav Desai, Socrates D. Vamvakos, Ritesh Saraf, Mahmud Hassan, Jason Yeung, Richard Rouse, Gurupada Mandal, K. C. Hsieh, Sanjay Dabral, Ying Cao, Prashant Choudhary, Chethan Rao, Karthisha Canagasaby

Publikováno v: Analog Integrated Circuits and Signal Processing. 78:259-273

This paper presents the design and Silicon verification of a 2.488---11.2 Gbps multi-standard SerDes transceiver in a 40 nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9eda7a109416d594abfeecdf1a3af8a0
https://doi.org/10.1007/s10470-013-0172-1

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A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications

Autor: Khaldoon Abugharbieh, Chethan Rao, Sanjay Dabral, Richard Rouse, Alvin Wang, Prashant Choudhary, Karthisha Canagasaby, Gurupada Mandal, Bendik Kleveland, K. C. Hsieh, Ritesh Saraf, Ying Cao, Mahmud Hassan, Claude R. Gauthier, Jason Yeung, Socrates D. Vamvakos, Shaishav Desai

Publikováno v: MWSCAS

The paper presents the design of a 2.488 – 11.2 Gbps SerDes transceiver in a 40nm low-leakage CMOS process. The paper explores the architectural and circuit techniques used to meet the stringent requirements of the high-speed SerDes and to mitigate

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6d84e261a54381fb88dd2548774b066c
https://doi.org/10.1109/mwscas.2012.6291943

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Power/Performance/Channel Length Tradeoffs in 1.6 to 9.6Gbps I/O Links in 90nm CMOS for Server, Desktop, and Mobile Applications

Autor: Santanu Chaudhuri, Vivek Joshi, Alok Tripathi, Mohiuddin Mazumder, J. Prijic, E. Yeung, Sanjay Dabral, K.S. Canagasaby, Pascal Meier

Publikováno v: 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

Performance and power of 1.6 to 9.6Gbps server, desktop, and mobile I/O links in a 1.2V 90nm CMOS test chip implementing equalized voltage-mode and current-mode drivers, TX and RX equalizers, self-biased ring oscillator and LC PLLs, and different RX

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4e932a5e2d23839e8f43443cfbedd9b7
https://doi.org/10.1109/vlsic.2006.1705321

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Jitter Amplification Characterization of Passive Clock Channels at 6.4 and 9.6 Gb/s

Autor: W. Anderson, James A. McCall, Santanu Chaudhuri, Sanjay Dabral, J. Bryan

Publikováno v: 2006 IEEE Electrical Performane of Electronic Packaging.

Jitter amplification characteristics of different forwarded clock channels at 6.4 and 9.6 Gb/s are illustrated with model correlations. The effect illustrates the need for quarter rate clocking at higher speed, in lossy serial links.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7dae19ed31aa8c70e94a28e7ac5354ac
https://doi.org/10.1109/epep.2006.321168

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Electrical validation of source synchronous chip-chip server links at 6.25 Gb/s

Autor: K.S. Canagasaby, Sanjay Dabral, Santanu Chaudhuri

Publikováno v: Electrical Performance of Electronic Packaging.

Modeling and validation of 6.25 Gb/s source synchronous backplane links is demonstrated using a correlation methodology. The link model predictions correlate within 10-25% error against scope measured eye and using on-die scope eye when the transmitt

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fa60b391940f695b9aea08e1f1526950
https://doi.org/10.1109/epep.2004.1407579

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Conference

Jitter Amplification Characterization of Passive Clock Channels at 6.4 and 9.6 Gb/s.

Autor: Santanu Chaudhuri, Warren Anderson, John Bryan, James McCall, Sanjay Dabral

Publikováno v: 2006 IEEE Electrical Performane of Electronic Packaging; 2006, p21-24, 4p

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