Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Sangyun Hwang"'
Autor:
Jaehyun Jeong, Jihun Oh, Hyoungjoong Kim, Soo-Min Lee, Joohee Shin, Jaehong Park, Sukhyun Jung, Kihwan Seong, Jongshin Shin, Sanghune Park, Kwanyeob Chae, Ju-young Kim, Kyoung-Hoi Koo, Sangyun Hwang, Shinyoung Yi, Eun-Su Kim
Publikováno v:
ISSCC
Recent emerging applications, such as autonomous vehicles, artificial intelligence, and deep learning, require a large amount of data computation. The GDDR6 interface is a candidate solution because it can operate up to 64GB/s (16Gb/s/pin x 32 pins)
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eeb20bfd3d8aca3b25bd63d1ff8ce889
https://doi.org/10.1109/isscc19947.2020.9062937
https://doi.org/10.1109/isscc19947.2020.9062937
Publikováno v:
Journal of the Korean Physical Society. 71:244-247
Resonant X-ray scattering measurements for a GdB4 single crystal have been carried out at Gd L 3- and L 2-edges. Branching ratios between x-ray scattering intensities at two x-ray energies are different for resonance peaks. Their analysis shows diffe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41bf5171717573025c58a7c3f5da4d79
https://doi.org/10.3938/jkps.71.244
https://doi.org/10.3938/jkps.71.244
Autor:
Joohee Shin, Billy Koo, Jongshin Shin, Kihwan Seong, Joo-hyung Lee, Won Lee, Jongryun Choi, Sanghune Park, Soo-Min Lee, Jinho Choi, Yoonjee Nam, Kwanyeob Chael, Sangyun Hwang, Seokkyun Ko, Shinyoung Yi, Hyungkwon Lee, Hyung-Jong Ko, Jihun Oh
Publikováno v:
VLSI Circuits
An all-digital 7.3Gb/s/pin LPDDR5 PHY is presented. A non-interruptive approximate delay compensation scheme is proposed to enhance tolerance to voltage variation without any memory access black-out. Thus, seamlessly maintained DQ-centering improves
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aef5fe2a575bcd7555723af27d4cbfd3
https://doi.org/10.23919/vlsic.2019.8777959
https://doi.org/10.23919/vlsic.2019.8777959
Publikováno v:
IEEE Signal Processing Letters. 11:463-466
This letter proposes a new distributed arithmetic (DA) algorithm for low-power finite-impulse response (FIR) filter implementation. The characteristic of the proposed algorithm is that the FIR filters using the proposed algorithm do not need to emplo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4b850d1a00aa69f3c1dc51128122b4b3
https://doi.org/10.1109/lsp.2004.824029
https://doi.org/10.1109/lsp.2004.824029
Publikováno v:
SoCC
In this paper, we present a SoC design of remote terminals for wireless telemetry system based on DS-CDMA technology. Wireless telemetry systems are data collecting system that gather the information data, such as temperature, pressure, humidity and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9e7755095545333f6629afcd2fd8ca75
https://doi.org/10.1109/socc.2004.1362462
https://doi.org/10.1109/socc.2004.1362462
Autor:
Sangyun Hwang, Jaeseok Kim
Publikováno v:
The 57th IEEE Semiannual Vehicular Technology Conference, 2003. VTC 2003-Spring..
This paper presents a new slot synchronization scheme robust to timing errors for W-CDMA when the slot synchronization scheme is performed using a resolution of two samples per chip. The proposed scheme uses the sum of consecutive complex matched fil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d2f873b8f9e50310ec5244daed3ebcc1
https://doi.org/10.1109/vetecs.2003.1207183
https://doi.org/10.1109/vetecs.2003.1207183
Publikováno v:
AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).
We propose a new architecture design for the Multicode CDMA (MC-CDMA) rake receiver. It contains one searcher module, three independent fat finger modules, and one combiner for the demodulation of high-rate data. We compare the hardware complexity of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85d6c8a7c378d9c0fde323a4fe9978c2
https://doi.org/10.1109/apasic.1999.824126
https://doi.org/10.1109/apasic.1999.824126
Publikováno v:
2003 5th International Conference on ASIC Proceedings (IEEE Cat No 03TH8690) ICASIC-03.
This paper presents a low-power digital IF (Intermediate Frequency) receiver using IIR (Infinite Impulse Response) filters for CDMA (Code Division Multiple Access) system. The proposed digital IF receiver is based on a conventional multi-stage decima
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30c8e5de42018581e934990af36a899d
https://doi.org/10.1109/icasic.2003.1277332
https://doi.org/10.1109/icasic.2003.1277332
Publikováno v:
GLOBECOM
The cell search scheme for W-CDMA consists of the following three stages: slot synchronization (stage 1), group identification and frame boundary detection (stage 2), and long code identification (stage 3). The performance of the cell search when a m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::211cd8d11f2905fd1305de5e22d3210f
https://doi.org/10.1109/glocom.2001.965988
https://doi.org/10.1109/glocom.2001.965988
Publikováno v:
IEEE International SOC Conference Proceedings, 2004; 2004, p355-358, 4p