Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Sanghune Park"'
Publikováno v:
2023 IEEE Custom Integrated Circuits Conference (CICC).
Autor:
Kwanyeob Chae, Jiyeon Park, Jaegeun Song, Billy Koo, Jihun Oh, Shinyoung Yi, Won Lee, Dongha Kim, Taekyung Yeo, Kyeongkeun Kang, Sangsoo Park, Eunsu Kim, Sukhyun Jung, Sanghune Park, Sungcheol Park, Mijung Noh, Hyogyuem Rhew, Jongshin Shin
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Autor:
Byoung-Joo Yoo, Lee Jae-Chol, Jongshin Shin, Dong-Ho Choi, Sanghune Park, Sang-Hyeok Chu, Michael Choi, Hyonguk Pang, Woo-chul Jung, Kim Bongkyu, Taehun Yoon, Hye-yeon Yang, Kang Gun-Il, Dong-Hyuk Lim, Seung-Yeob Baek, Naxin Kim, Kang-Jik Kim, Young-Ho Choi, Lee June-Hee
Publikováno v:
ISSCC
Needs for I/O bandwidth have rapidly increased with the explosive growth of internet traffic and data technologies. To accommodate the required high bandwidth, a DSP-based PAM-4 transceiver became the most robust solution with increased usage of chan
Autor:
Jaehyun Jeong, Jihun Oh, Hyoungjoong Kim, Soo-Min Lee, Joohee Shin, Jaehong Park, Sukhyun Jung, Kihwan Seong, Jongshin Shin, Sanghune Park, Kwanyeob Chae, Ju-young Kim, Kyoung-Hoi Koo, Sangyun Hwang, Shinyoung Yi, Eun-Su Kim
Publikováno v:
ISSCC
Recent emerging applications, such as autonomous vehicles, artificial intelligence, and deep learning, require a large amount of data computation. The GDDR6 interface is a candidate solution because it can operate up to 64GB/s (16Gb/s/pin x 32 pins)
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 65:789-793
A power reduction scheme that uses ac termination at receiver (RX) and a transmitter (TX) output driver with an active inductor part (AIP) is proposed for a point-to-point post-low-power mobile DRAM4 interface at 8 Gb/s. AC termination at the RX I/O
Autor:
Joohee Shin, Billy Koo, Jongshin Shin, Kihwan Seong, Joo-hyung Lee, Won Lee, Jongryun Choi, Sanghune Park, Soo-Min Lee, Jinho Choi, Yoonjee Nam, Kwanyeob Chael, Sangyun Hwang, Seokkyun Ko, Shinyoung Yi, Hyungkwon Lee, Hyung-Jong Ko, Jihun Oh
Publikováno v:
VLSI Circuits
An all-digital 7.3Gb/s/pin LPDDR5 PHY is presented. A non-interruptive approximate delay compensation scheme is proposed to enhance tolerance to voltage variation without any memory access black-out. Thus, seamlessly maintained DQ-centering improves
Publikováno v:
ISOCC
This paper presents practical high-speed and low-power design methodologies for digital PHY in deep sub-micron technologies. The standard-cell-based design approaches with automated place and route shorten the design time dramatically. In addition, r
Autor:
Kyoung-Hoi Koo, Sang-Soo Park, Eun-Su Kim, Sanghune Park, Dae-Ro Kim, Soo-Min Lee, Suho Kim, Sungho Park, Sanghyun Lee, Lee Hyung-Kweon, Jinho Choi, Seokkyun Ko, Kwanyeob Chae, Yoonjee Nam, Sukhyun Jung, Jihun Oh, Jongryun Choi
Publikováno v:
ISSCC
Although the LPDDR4 interface has enabled industry requirements, such as low power consumption and high bandwidth, additional evolution of the current LPDDR4 performance is expected. To respond to the need for more power efficient devices with higher
Autor:
Hyun-Hyuck Kim, Kwanyeob Chae, Won Lee, Sanghyun Lee, Sanghune Park, Jinho Choi, Hyungkwon Yi, Yoonjee Nam, Sang Hoon Joo, Jongryun Choi, Shinyoung Yi
Publikováno v:
ESSCIRC
This paper presents a 4.4Gbps/pin all-digital LPDDR4 PHY with a bit-slice architecture in 10nm FinFET process technology. The proposed bit-slice architecture includes new I/O structure for area reduction without any off-chip performance degradation a
Autor:
K.T. Kim, Sanghune Park, J.H. Ko, Lee Juyeong, J Bae, A.R. Koh, J.W. Bae, Joong Sub Choi, W.M. Lee
Publikováno v:
Journal of Minimally Invasive Gynecology. 20:S186