Zobrazeno 1 - 10
of 38
pro vyhledávání: '"Sang-pil Sim"'
Autor:
Woojin Rim, Sunghyun Park, Sanghoon Baek, Young-Keun Lee, Jong-Hoon Jung, Jong Shik Yoon, Gyu-Hong Kim, Jae-Hong Park, Giyong Yang, Jinsuk Jung, Kyu-Myung Choi, Sang-Kyu Oh, Jae-Ho Park, Sang-pil Sim, Hyo-sig Won, Sung-Bong Kim, Jin-Tae Kim, Kang-Hyun Baek, Taejoong Song, Yongho Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:158-169
Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 $\mu$ m $^{2}$ and a 0.080 $\mu$ m $^{2}$ 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve ${\rm V}_{{\
Publikováno v:
IEEE Transactions on Electron Devices. 50:1501-1510
In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we prop
Publikováno v:
Solid-State Electronics. 46:153-156
Channel electron and hole mobilities in MOSFETs have been extracted in terms of the effective vertical field for several substrate biases. After ascertaining that the 2-D drift–diffusion numerical device simulator is reproducing the substrate charg
Autor:
Kyu-Myung Choi, Jong-Hoon Jung, Woojin Rim, Sunghyun Park, Jinsuk Jung, Sung-Bong Kim, Gyu-Hong Kim, Jae-Ho Park, Sanghoon Baek, Young-Keun Lee, Jin-Tae Kim, Sang-pil Sim, Jong Shik Yoon, Kee Sup Kim, Giyong Yang, Taejoong Song, Sang-Kyu Oh, Kang-Hyun Baek
Publikováno v:
ISSCC
With the explosive growth of battery-operated portable devices, the demand for low power and small size has been increasing for system-on-a-chip (SoC). The FinFET is considered as one of the most promising technologies for future low-power mobile app
Publikováno v:
IEEE Electron Device Letters. 23:740-742
The effect of random signal lines on the on-chip inductance is quantitatively investigated, using an S-parameter-based methodology and a full wave solver, leading to an empirical model for high-frequency inductance. The results clearly indicate that
Autor:
D. K. Sohn, Y.K. Bae, Y.D. Lim, Yohan Kim, J.G. Hong, C. Ryou, Soon-yeon Park, C.G. Koh, Jae Gon Lee, Jung-Chak Ahn, S. Hyun, Byung-chan Lee, Sangjoo Lee, Yang-Soo Son, D.H. Cha, C.L. Cheng, Sung-dae Suk, S.W. Nam, H.-J. Cho, J.S. Yoon, Won-Jun Jang, M. Sadaaki, Ming Li, S.H. Hong, Wouns Yang, Sang-pil Sim, Dong-Won Kim, S. Choi, Jung-In Hong, Won-Cheol Jeong, B. U. Yoon, Hwa-Sung Rhee, Min-Sang Kim, Chilhee Chung, Daphnee Hui Lin Lee, Sang-Bom Kang, Kang-ill Seo, Hee-Soo Kang
Publikováno v:
2011 International Electron Devices Meeting.
A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA
Autor:
Kang-ill Seo, Jongwan Choi, Sang-pil Sim, Yangsoo Sohn, Seung-Hun Lee, Kwan-Heum Lee, Si-Young Choi, Chulgi Song, Kyungseok Oh, Junghyun Park, Choongryul Ryu, Tae-Ouk Kwon, Chilhee Chung, Hyun-Jung Lee, Sang Bom Kang, Hee-Kyung Jeon, Wookje Kim, Seok-Hoon Kim, Kwan-Yong Lim, Uihui Kwon, Hong-Sik Yoon, Chung Geun Koh, Jinyeong Cho, Eunha Lee
Publikováno v:
2010 International Electron Devices Meeting.
High-k/metal gate (HKMG) compatible high performance Source/Drain (S/D) stress-memorization-technology (SMT) is presented. Channel stress generated by SMT can be simulated by using mask-edge dislocation model, which is consistent with the measured ac
Publikováno v:
IEEE Transactions on Electron Devices. 38:1905-1912
Experimental and theoretical studies of the gate field dependencies of the low-field mobilities of electrons and holes show that by changing surface orientations and oxidation conditions the two-dimensional electron gas formulation can successfully e
Autor:
Jeehoon Han, Sang-pil Sim, Chaemyung Chang, Chan-Kwang Park, Kinam Kim, Jung-In Han, Bongyong Lee, Wook-Hyun Kwon
Publikováno v:
2006 IEEE International Integrated Reliability Workshop Final Report.
Sporadic drain disturb problem in multi-level cell (MLC) NOR flash memory devices incorporating cobalt salicidation processes becomes a new critical failure mode. The provoked disturb is shown to be caused by erratic lateral encroachment of cobalt sa
Autor:
Jaehoon Kim, Bongyong Lee, Ki-Yeol Byun, Chan-Kwang Park, Sang-pil Sim, Wook-Hyoung Lee, Kinam Kim
Publikováno v:
2006 European Solid-State Device Research Conference.
This paper describes the key technology to realize a scaled multilevel NOR flash memory with an improved gate oxide integrity. It is found that a thin poly-Si employed in STI formation is a good buffer layer to prevent the oxide local thinning at STI