Zobrazeno 1 - 10 of 32 pro vyhledávání: '"Sang-Jun Hwang"'
7
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion
Autor: Seong-Jin Jang, Young-Hyun Jun, Young-Chul Cho, Kyoung-Ho Kim, Soo-In Cho, Joo Sun Choi, Jeong-Don Ihm, Min-Sang Park, Hong-Kyong Lee, Seung-Jun Bae, Kwang-Il Park, Jae-Sung Kim, Gil-Shin Moon, Ho-young Song, Hyun-Jin Kim, Yoon-Sik Park, Dae Hyun Kim, Ji-Hoon Lim, Sang-Jun Hwang, Sam-Young Bang, Woojin Lee, Sung-Hoon Kim, Kinam Kim, Seok-Won Hwang
Publikováno v: IEEE Journal of Solid-State Circuits. 43:121-131
4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::dce0add1cead67dc39fa68f62ad1b5fa
https://doi.org/10.1109/jssc.2007.908002
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8
Double-Dose, New-Generation Proton Pump Inhibitors Do Not Improve Helicobacter pylori Eradication Rate
Autor: Dong Il Park, Jung Sik Park, Sang Jun Hwang, Hong Joo Kim, Hyo Sun Choi, Byung Ik Kim, Yong Kyun Cho, Woo Kyu Jeon, Chong Il Sohn
Publikováno v: Helicobacter. 12:638-642
Background: Up to present, omeprazole plus two antibiotics are used for Helicobacter pylori eradication therapy . Few studies have compared double-dose new-generation, proton pump inhibitors (PPI) with omeprazole. Therefore, we conducted a randomized
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5cd743687a9b7497424faa5e41985f1b
https://doi.org/10.1111/j.1523-5378.2007.00556.x
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10
A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control
Autor: Ho-kyoung Lee, Jin-seok Kwak, Y.S. Park, Seok-Won Hwang, Woojin Lee, Yu-Rim Lee, Seok-Jung Kim, Min-Sang Park, Soo-In Cho, Seong-Jin Jang, Sang-Jun Hwang, Sang-Bo Lee, Jong-Soo Lee, Young-Hyun Jun, Seong-Ho Cho, Hyoung-Jo Heo, Young-Uk Jang, Young-Cheol Cho, Won-Hwa Shin
Publikováno v: IEEE Journal of Solid-State Circuits. 40:223-232
An 8 M /spl times/ 32 GDDR (graphic DDR) SDRAM operating up to 800-MHz clock (CLK) frequency is described. The GDDR SDRAM demands an effective control of CAS latency due to the large and wide number of CAS latencies at the CLK frequency. A wave-pipel
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::39bbf74283e557e6d57841eaacb3427a
https://doi.org/10.1109/jssc.2004.837983
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