Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Sang-Hye Chung"'
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 63:264-268
This brief presents a power-efficient forwarded-clock receiver that is tolerant to high-frequency jitter by mixing filtered clock jitter to data. Due to mixing the filtered clock jitter, the proposed receiver does not include power-hungry delay lines
Autor:
Sang-Hye Chung, Lee-Sup Kim
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:2023-2033
In this paper, a data-jitter mixing (DJM) forwarded-clock receiver is proposed that achieves high jitter correlation between data and a clock for high speed and small power consumption. The first-stage injection-locked oscillator (ILO) filters out hi
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 62:2495-2503
This paper presents a forwarded-clock receiver using a mixing cell integrated injection-locked oscillator (MIILO) and an I/Q generator based on injection-locked oscillator (IQGILO). By using MIILO, jitter tolerance is enhanced by about 1.8 times at h
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 61:2482-2490
This paper presents a quarter-rate forwarded clock (FC) receiver based on an injection-locked oscillator (ILO) which exploits a phenomenon in which phases of the output clock are shifted by the duty-cycle of an injection clock. Also, this paper descr
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 61:153-157
A source synchronous architecture with constant and wide jitter-tracking bandwidth (JTB) is presented. The proposed receiver is based on an injection-locked oscillator (ILO), which provides jitter filtering and phase deskew simultaneously. While usin
Autor:
Lee-Sup Kim, Seok-Hoon Kim, Kyusik Chung, Sung-Eui Yoon, Young Jun Kim, Hong-Yun Kim, Sang-Hye Chung
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:1082-1093
A mobile 3-D display processor with a subdivider is presented for higher visual quality on handhelds. By combining a subdivision technique with a 3-D display, the processor can support viewers see realistic smooth surfaces in the air. However, both t
Autor:
Young-Ju Kim, Sang-Hye Chung, Seung-Jun Bae, Ji-Hwan Seol, Jung-Bae Lee, Lee-Sup Kim, Kyung-Soo Ha, Joo Sun Choi
Publikováno v:
ISSCC
For chip-to-chip parallel interfaces, maintaining low power consumption while achieving high aggregate bandwidth is the key trend. Forwarded-clock (FC) architecture is well suited to this trend because of the simple structure and inherent correlation
Autor:
Sang-Hye Chung, Lee-Sup Kim
Publikováno v:
VLSIC
This paper presents a data jitter mixing forwarded-clock receiver which is robust against power supply induced jitter (PSIJ) and overcomes 1.92ns latency mismatch between data and clock. The forwarded-clock architecture has a tradeoff between the num
Publikováno v:
CICC
This paper presents a forwarded clock receiver based on an injection-locked oscillator (ILO) with a simple clock multiplication unit to reduce the clock jitter and power consumption. The clock multiplication unit employs AC coupling and superposition
Publikováno v:
ISCAS
An area-efficient dynamic thermal management (DTM) unit using multiplying delay-locked loop (MDLL) with shared DLL scheme is proposed for per-core DTM in many-core processors. The proposed DTM unit consists of a MDLL and a shared-DLL-based temperatur