Zobrazeno 1 - 10
of 31
pro vyhledávání: '"Sang Phill Park"'
Autor:
Sang Phill Park, Ulya R. Karpuzcu, Nitin Borkar, Dinesh Somasekhar, Ayan Paul, Young Moon Kim, Chris H. Kim
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24:3468-3476
In this paper, we study two different ON-chip power delivery schemes, namely, fully integrated voltage regulator (FIVR) and low-dropout regulator (LDO), and analyze their effect on total system power under process variation, assuming a realistic dyna
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a9263380f1c859d1f724e16723e5673
https://doi.org/10.1109/tvlsi.2016.2555954
https://doi.org/10.1109/tvlsi.2016.2555954
Autor:
Niladri Narayan Mojumder, Kaushik Roy, Charles Augustine, Xuanyao Fong, Sang Phill Park, Sri Harsha Choday
Publikováno v:
IEEE Sensors Journal. 12:756-766
Electron-spin based data storage for on-chip memories has the potential for ultrahigh density, low power consumption, very high endurance, and reasonably low read/write latency. In this article, we analyze the energy-performance characteristics of a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4180d7352a9c54fa70b3b73110c342cc
https://doi.org/10.1109/jsen.2011.2124453
https://doi.org/10.1109/jsen.2011.2124453
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20:248-256
Radiation-induced soft error rate (SER) degrades the reliability of static random access memory (SRAM)-based field programmable gate arrays (FPGAs). This paper presents a new built-in 2-D Hamming product code (2-D HPC) scheme to provide reliable oper
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2dd30b6118667f25bc507b3f11b47b11
https://doi.org/10.1109/tvlsi.2010.2095435
https://doi.org/10.1109/tvlsi.2010.2095435
Publikováno v:
IEEE Transactions on Electron Devices. 58:3837-3846
In this paper, we present tri-mode independent-gate (IG) FinFETs for dynamic voltage/frequency scalable 6T SRAMs. The proposed design exploits the fact that the spacer patterning technology, used for FinFET fabrication, offers the same device footpri
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::00a7ea4d28fc16d472f74fa28fb7bdd2
https://doi.org/10.1109/ted.2011.2166117
https://doi.org/10.1109/ted.2011.2166117
Publikováno v:
IEEE Electron Device Letters. 35:488-490
A novel nonvolatile flip-flop (NVFF) using a magnetic tunnel junction (MTJ) is presented for power gating architecture. The proposed NVFF exploits spin Hall effect (SHE) for fast and low-power data backup into MTJs before the power is gated off. Owin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::42e7ce0cee57728379ab9f88e3bc3894
https://doi.org/10.1109/led.2014.2304683
https://doi.org/10.1109/led.2014.2304683
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:270-280
Performance variability in digital integrated circuits can largely affect parametric yield and product reliability in ultra deep submicrometer technologies. As a result, variation resilience is becoming an essential design requirement for future tech
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b4bbdbc72fc7466372dec5d674d0abf
https://doi.org/10.1109/tvlsi.2008.2010399
https://doi.org/10.1109/tvlsi.2008.2010399
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:401-410
Supply voltage scaling is one of the easiest ways to reduce energy dissipation. Therefore, researchers have considered subthreshold logic as a promising option to achieve ultra low energy dissipation. However, circuit propagation delay is extremely s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5cbcb929d98caa10d0390b98d4c5b60c
https://doi.org/10.1109/jssc.2009.2036764
https://doi.org/10.1109/jssc.2009.2036764
Publikováno v:
IEEE Design & Test of Computers. 26:8-17
Bias temperature instability (BTI) is one of the major reliability challenges in nanoscale CMOS technology. This article investigates the severity of such degradation in logic and memory circuits. The simulation results reveal that BTI poses severe c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7a54598f587fb91f49c1d5aef3842c9
https://doi.org/10.1109/mdt.2009.154
https://doi.org/10.1109/mdt.2009.154
Publikováno v:
ISLPED
Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for high integration density and excellent scalability. Despite the attractive features, high write current and power is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::be0f6b5ac00b7ac6a83551379ab38251
https://doi.org/10.1145/2333660.2333664
https://doi.org/10.1145/2333660.2333664
Autor:
Sang Phill Park, Kaushik Roy, Sumeet Kumar Gupta, Niladri Narayan Mojumder, Anand Raghunathan
Publikováno v:
DAC
Spin-transfer torque magnetic RAM (STT MRAM) has emerged as a promising candidate for on-chip memory in future computing platforms. We present a cross-layer (device-circuit-architecture) approach to energy-efficient cache design using STT MRAM. At th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2d3644dc2fcab838be2ea652e58712e2
https://doi.org/10.1145/2228360.2228447
https://doi.org/10.1145/2228360.2228447