Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Samuel Bayliss"'
Autor:
Abhishek Kumar Jain, Stephen Neuendorffer, Kristof Denolf, Samuel Bayliss, Alireza Khodamoradi
Publikováno v:
IEEE Circuits and Systems Magazine. 21:75-96
With the continued slowing of Moore?s law and Dennard scaling, it has become more imperative that hardware designers make the best use of domain-specific information to improve designs. Gone are the days when we could rely primarily on silicon proces
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::99ef27203b52cd50d12fcafbb816a67e
https://doi.org/10.1109/mcas.2021.3071629
https://doi.org/10.1109/mcas.2021.3071629
Publikováno v:
HPEC
Xilinx's AI Engine is a recent industry example of energy-efficient vector processing that includes novel support for 2D SIMD datapaths and shuffle interconnection network. The current approach to programming the AI Engine relies on a C/C++ API for v
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4a27ecee4de7615459571e7939651f36
https://doi.org/10.1109/hpec43674.2020.9286183
https://doi.org/10.1109/hpec43674.2020.9286183
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 37:1802-1815
Loop pipelining is one of the most important optimization methods in high-level synthesis (HLS) for increasing loop parallelism. There has been considerable work on improving loop pipelining, which mainly focuses on optimizing static operation schedu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0a3ba1d936c33660922c6f3d50db417b
https://doi.org/10.1109/tcad.2017.2783363
https://doi.org/10.1109/tcad.2017.2783363
Publikováno v:
ACSSC
52nd Annual Asilomar Conference on Signals, Systems, and Computers
52nd Annual Asilomar Conference on Signals, Systems, and Computers
As a key optimisation method in high-level synthesis (HLS), high-performance loop pipelining is enabled by the static scheduling algorithm. When there are non-trivial memory dependencies in the loop, current HLS tools have to apply conservative pipel
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::3020dec80de0ff5deff1beed4638b09c
https://doi.org/10.1109/acssc.2017.8335151
https://doi.org/10.1109/acssc.2017.8335151
Autor:
Samuel Bayliss, Nachiket Kapre
Publikováno v:
FPL
High-performance FPGA programming has typically been the exclusive domain of a small band of specialized hardware developers. They are capable of reasoning about implementation concerns at the register-transfer level (RTL) which is analogous to assem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f27bcbd63b4825d6cd0376b8e5a6f260
https://doi.org/10.1109/fpl.2016.7577380
https://doi.org/10.1109/fpl.2016.7577380
Publikováno v:
Microprocessors and Microsystems. 36:665-675
SDRAM memories are a commodity technology which deliver fast, cheap and high capacity external memory in many cost-sensitive embedded applications. When designing with SDRAM memory, the memory bandwidth available is strongly dependent on the sequence
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5917b3fbb18e903a14e6aa6e1e4054ad
https://doi.org/10.1016/j.micpro.2012.05.007
https://doi.org/10.1016/j.micpro.2012.05.007
Publikováno v:
FCCM
Loop pipelining is probably the most important optimization method in high-level synthesis (HLS), allowing multiple loop iterations to execute in a pipeline. In this paper, we extend the capability of loop pipelining in HLS to handle loops with uncer
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::88f9a1fc4fd112d516c17b449e81b5ca
https://doi.org/10.1109/fccm.2015.31
https://doi.org/10.1109/fccm.2015.31
Publikováno v:
FPGA
Memory-intensive implementations often require access to an external, off-chip memory which can substantially slow down an FPGA accelerator due to memory bandwidth limitations. Buffering frequently reused data on chip is a common approach to address
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2750a456f715d94dbd3797b624cce76d
https://doi.org/10.1145/2684746.2689073
https://doi.org/10.1145/2684746.2689073
Publikováno v:
DAC
Digital circuits are currently designed to ensure timing closure. Releasing this constraint by allowing timing violations could lead to significant performance improvements, but conventional forms of computer arithmetic do not fail gracefully when pu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe5fb4206f88498371afb4525a0a6806
https://doi.org/10.1145/2593069.2593118
https://doi.org/10.1145/2593069.2593118