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pro vyhledávání: '"Samary Baranov"'
Autor:
Samary Baranov
Publikováno v:
IFAC Proceedings Volumes. 42:160-165
High level synthesis, implemented in the experimental EDA tool Abelite is based on Algorithmic State machine (ASM) transformations (composition, minimization, extraction, etc.), special algorithms for Data Path and Control Unit design and a very fast
Autor:
Samary Baranov
Logic Synthesis for Control Automata provides techniques for logic design of very complex control units with hardly any constraints on their size, i.e. the number of inputs, outputs and states. These techniques cover all stages of control unit design
Publikováno v:
LATW
This paper presents a new approach for synthesizing hardware checkers from temporal assertions described in Property Specification Language (PSL). The approach utilizes Algorithmic State Machines (ASMs) based High Level Synthesis (HLS) tool ABELITE.
Autor:
Samary Baranov, L. Bregman
Publikováno v:
Journal of Microcomputer Applications. 17:227-237
Techniques for logic synthesis of control units from elements with given constraints on their complexity are presented. Programmable logic arrays (PLA) with restrictions on the number of inputs, outputs and terms are used as an example of such elemen
Publikováno v:
EWDTS
The paper presents an approach for integration of automatic test bench generation based on a hierarchical test pattern generator Decider into the high-level synthesis flow Abelite. While the high-level synthesis flow provides fast results of complex
Autor:
Samary Baranov
Publikováno v:
Design of Digital Systems and Devices ISBN: 9783642175442
The most complicated stage of each design, namely the system design, is discussed. An example of the design for a rather simple processor is shown. A design procedure is proposed, which included such steps as combination of separate algorithmic state
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::adf0407254da9c65d16af8758d92d8cd
https://doi.org/10.1007/978-3-642-17545-9_1
https://doi.org/10.1007/978-3-642-17545-9_1
Publikováno v:
IOLTS
The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area and the number of crosspoint devices, are considered
Autor:
Samary Baranov
Publikováno v:
EUROMICRO
Control unit design is the main problem in the design of digital systems. It is popular to use algorithmic state machine (ASM) to describe a behavior of a control unit. We present efficient techniques for minimization of the number of vertices in ASM
Autor:
Samary Baranov
Publikováno v:
Proceedings Second EUROMICRO Workshop on Advanced Mobile Robots.
To design a control unit for a mobile robot, the finite state machine (FSM) describing the behavior of such a robot should be constructed. As a rule, it is difficult to construct an optimal FSM to represent a complex behavior of the mobile robot cont
Autor:
Samary Baranov
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540649489
FPL
FPL
For hardware realization of computer programs (for the realization of software as hardware) it is very important to represent, to transform and to synthesize very complex Finite State Machines (FSM). This work contains the first report about CAD syst
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0c5fd445123bf9c4bd5229c55650d896
https://doi.org/10.1007/bfb0055239
https://doi.org/10.1007/bfb0055239