Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Saman M. I. Adham"'
Publikováno v:
VLSI-DAT
A physically unclonable function (PUF) targeting internet of things is implemented in 28nm CMOS. By filtering, the reliability of a PUF is improved leading to lower overhead. Measured results show that the proposed design can operate correctly at tem
Autor:
Ching-Fang Chen, Saman M. I. Adham, Chin-Ming Fu, Wen-Hung Huang, Chih-Hsien Chang, Tien-Chien Huang, Mao-Hsuan Chou, Tze-Chiang Huang, Ying-Yu Hsu, Chien-Chun Tsai, William Wu Shen, Min-Jer Wang, Mu-Shan Lin, Ashok B. Mehta, Shu-Chun Yang
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:1063-1074
A 1 Tbit/s bandwidth PHY is demonstrated through CoWoS™ platform. Two chips: SOC and embedded DRAM (eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/s with VDDQ
Publikováno v:
ITC
Silicon foundries are enabling fab-less chip design companies to meet market demand of highly integrated devices as mobile applications are flourishing in recent years. Foundries are also enabling other sectors of the semiconductor industry to provid
Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs
Publikováno v:
VLSI-DAT
To meet power, performance and area requirements of modern electronic products, heterogeneous system integration where dies implemented in dedicated, optimized process technologies are stacked together to form a system is inevitable. The use of known
Autor:
Hung-Chih Lin, Hao Chen, Saman M. I. Adham, Mincent Lee, Ching-Nen Peng, Min-Jer Wang, Sen-Kuei Hsu
Publikováno v:
VLSI-DAT
Three-dimension ICs (3D-ICs) are the current trend due to their improvement in heterogeneous integration, performance, power consumption, silicon area, and form factors. However, the consequent new challenges are interconnects between dies, i.e., Thr
Autor:
Tze-Chiang Huang, Jungi Choi, Vivek Chickermane, Hayden Hyungdong Lee, Min-Jer Wang, Saman M. I. Adham, Sandeep Kumar Goel, Sangdoo Kim, Ashok B. Mehta, Subhasish Mukherjee, Ji-Jan Chen, Brion Keller, Jeongho Cho, Navdeep Sood, Thomas Valind, Frank Lee
Publikováno v:
Handbook of 3D Integration
Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D for
Publikováno v:
DATE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitors all gate output swings and flags all abnormal voltage excursions. The