Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Sam-Young Bang"'
Autor:
Chang-Yong Lee, Seung-Jun Bae, Jeong-Woo Lee, Seung-Hoon Oh, Yong-Hun Kim, Young-Soo Sohn, Gyo-Young Jin, Gong-Heum Han, Dong-seok Kang, Young-Hun Seo, Gun-hee Cho, Seung-Hyun Cho, Sam-Young Bang, Seong-Jin Jang, Youn-sik Park, Yong-Jun Kim, Kwang-Il Park, Jung-Hwan Choi, Seouk-Kyu Choi, Kyung-Bae Park, Sung-Geun Do, Young-Ju Kim, Keon-woo Park, Ji-Hak Yu, Jae-Sung Kim, Su-Yeon Doo, Jae-Koo Park, Chan-Yong Lee, Chang-Ho Shin, Hye-Jung Kwon, Byung-Cheol Kim, Hyuk-Jun Kwon, Sang-Sun Kim, Min-Su Ahn, Hyun-Soo Park, Chul-Hee Jeon, Lee Yong-Jae, Ki-Hun Yu, Sang-Yong Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:197-209
The graphic DRAM standard GDDR6 is developed to overcome the limitation of previous standards GDDR5/5X for achieving high-speed operation. This paper introduces 16-Gb GDDR6 DRAM with a per-bit trainable single-ended decision feedback equalizer (DFE),
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d08bc4f852cc052f17c7e89b51e1192
https://doi.org/10.1109/jssc.2018.2883395
https://doi.org/10.1109/jssc.2018.2883395
Autor:
Lee Yong-Jae, Seung-Hyun Cho, Kyung-Bae Park, Seong-Jin Jang, Jong-Ho Lee, Min-Woo Won, Su-Yeon Doo, Youngseok Lee, Jung-Bum Shin, Youn-sik Park, Hyun-Soo Park, Jae-Sung Kim, Kwang-Il Park, Keon-woo Park, Sang-Yong Lee, Chul-Hee Jeon, Yoon-Joo Eom, Dong-seok Kang, Yong-Hun Kim, Ki-Hun Yu, Jae-Koo Park, Chan-Yong Lee, Sang-Hoon Jung, Yong-Jun Kim, Young-Soo Sohn, Gun-hee Cho, Jung-Hwan Choi, Seung-Jun Bae, Chang-Yong Lee, Sang-Sun Kim, Beob-Rae Cho, Chang-Ho Shin, Seung-Hoon Oh, Young-Sik Kim, Byeong-Cheol Kim, Yoon-Gue Song, Sung-Geun Do, Hyuk-Jun Kwon, Young-Ju Kim, Sam-Young Bang, Ji-Suk Kwon, Min-Su Ahn, Young-Hun Seo, Hyung-Kyu Kim, Jeong-Woo Lee, Gong-Heum Han, Ji-Hak Yu, Hye-Jung Kwon, Seouk-Kyu Choi
Publikováno v:
ISSCC
Starting at 512Mb 6Gb/s/pin [1], GDDR5's speed and density have been steadily developing for about 10 years; recently achieving 8Gb 9Gb/s/pin [2] with per-pin timing training. Although 8Gb GDDR5X can operate at 12Gb/s [3] by increasing the burst leng
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b3314102637da5c0ef4d2bd3d784505
https://doi.org/10.1109/isscc.2018.8310255
https://doi.org/10.1109/isscc.2018.8310255
Autor:
Yong-Ki Cho, Dong-Min Kim, Seung-Jun Bae, Young-Sik Kim, Hyang-ja Yang, Sang-hyup Kwak, Beom-Sig Cho, Jae-Young Lee, Tae-Young Oh, Hye-Ran Kim, Byeong-Cheol Kim, Cheol-Goo Park, Yun-Seok Yang, Jeong-Don Lim, Chang-Ho Shin, Seok-Won Hwang, Min-Sang Park, Sam-Young Bang, Ji-Hoon Lim, Young-Ryeol Choi, Joo Sun Choi, Jin-Kook Kim, Dae Hyun Kim, Young-Hyun Jun, Gil-Shin Moon, Kwang-Il Park, Young-Soo Sohn, Jae-Hyung Lee, Jin-Hyun Kim, Hyun-Joong Kim
Publikováno v:
ISSCC
In the development of 3D graphic systems for higher resolution and more realistic modeling and rendering, graphic memories also have been playing a critical role to offer the required high bandwidth. Currently, GDDR5 SDRAM's provide with 7Gbps per pi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e1e0da4c841439d92cfbcf9c01b5b179
https://doi.org/10.1109/jssc.2010.2085991
https://doi.org/10.1109/jssc.2010.2085991
Autor:
Seong-Jin Jang, Young-Hyun Jun, Young-Chul Cho, Kyoung-Ho Kim, Soo-In Cho, Joo Sun Choi, Jeong-Don Ihm, Min-Sang Park, Hong-Kyong Lee, Seung-Jun Bae, Kwang-Il Park, Jae-Sung Kim, Gil-Shin Moon, Ho-young Song, Hyun-Jin Kim, Yoon-Sik Park, Dae Hyun Kim, Ji-Hoon Lim, Sang-Jun Hwang, Sam-Young Bang, Woojin Lee, Sung-Hoon Kim, Kinam Kim, Seok-Won Hwang
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:121-131
4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dce0add1cead67dc39fa68f62ad1b5fa
https://doi.org/10.1109/jssc.2007.908002
https://doi.org/10.1109/jssc.2007.908002
Publikováno v:
SLIP
3D interconnect between two dies can span a wide range of bandwidths and region areas, depending on the application, partitioning of the dies, die size, and floorplan. We explore the concept of dividing such an interconnect into local clusters, each
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::be697b9453f4bfedc3c042f242ed1832
https://doi.org/10.1109/slip.2015.7171709
https://doi.org/10.1109/slip.2015.7171709
Autor:
Gil-Shin Moon, Jeong-Don Lim, Hyang-ja Yang, Seung-Jun Bae, Dae Hyun Kim, Hye-Ran Kim, Woo-Seop Kim, Byeong-Cheol Kim, Dong-seok Kang, Cheol-Goo Park, Yong-Ki Cho, Yong-Jae Shin, Yun-Seok Yang, Gong-Heom Han, Young-Soo Sohn, Chang-Ho Shin, Min-Sang Park, Si-Hong Kim, Joo Sun Choi, sunyoung park, Ho-Seok Seol, Kwang-Il Park, Sam-Young Bang, Tae-Young Oh, Young-Ryeol Choi, Su-Yeon Doo, Young-Hyun Jun, Sang-hyup Kwak, Young-Sik Kim
Publikováno v:
ISSCC
Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utili
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::17f134797a9a27620a368d25d78b0da6
https://doi.org/10.1109/isscc.2011.5746414
https://doi.org/10.1109/isscc.2011.5746414
Autor:
Hwan-Wook Park, Sang-hyup Kwak, Kwang-Il Park, Dong-Min Kim, sunyoung park, Jae-Young Lee, Young-Hyun Jun, Tae-Young Oh, Yoo-seok Yang, Su-Yeon Doo, Woo-Seop Kim, Jin-Il Lee, Seung-Jun Bae, Dae Hyun Kim, Hyang-ja Yang, Ki-Woong Yeom, Sam-Young Bang, Young-Soo Sohn, Joo Sun Choi, Young-Sik Kim
Publikováno v:
2010 Symposium on VLSI Circuits.
A 7Gb/s single ended transceiver with low jitter and ISI is implemented in 40nm DRAM process. DRAM optimized LC PLL achieves inductor Q of 3.86 and results in random jitter of 670fs rms. A clock tree regulator with closed loop replica path reduces lo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::030894434ce2c1f8a7039ec69b775251
https://doi.org/10.1109/vlsic.2010.5560300
https://doi.org/10.1109/vlsic.2010.5560300
Autor:
Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun-Joong Kim, Jin-Hyun Kim, Jin-Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae-Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seok-Won Hwang, Jeong-Don Lim, Kwang-Il Park, Joo Sun Choi, Young-Hyun Jun
Publikováno v:
2010 IEEE International Solid-State Circuits Conference - (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6cc843d5d0e2c1ef2d41021d7b3bedcf
https://doi.org/10.1109/isscc.2010.5433889
https://doi.org/10.1109/isscc.2010.5433889
Autor:
Ki-Woong Yeom, Seung-Jun Bae, Seong-Jin Jang, Hye-Ran Kim, Dae-Hyun Chung, Cheol-Goo Park, Gil-Shin Moon, Hyang-ja Yang, Joo Sun Choi, Jae-Sung Kim, Jae-Young Lee, Min-Sang Park, Kyoung-Ho Kim, Kwang-ll Park, Dae Hyun Kim, Kang-Young Kim, Jingook Kim, Young-Hyun Jun, Yong-Jae Shin, Young-Soo Sohn, Sam-Young Bang, Si-Hong Kim, Jae-Hyung Lee, Kinam Kim, Ho-Kyung Lee, In-Soo Park
Publikováno v:
ISSCC
Demand for high-speed DRAM in graphics application pushes a single-ended I/O signaling to operate up to 6Gb/s. To maintain the speed increase, the GDDR5 specification shifts from GDDR3/4 with respect to forwarded clocking, data training for write and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7f59fae5256fcdac88c998be8845e2e0
https://doi.org/10.1109/isscc.2008.4523165
https://doi.org/10.1109/isscc.2008.4523165
Autor:
Jae-Sung Kim, Ho-young Song, Su-Jin Park, Sang-Jun Hwang, Sam-Young Bang, Young-Chul Cho, Seong-Jin Jang, Soo-In Cho, Sung-Hoon Kim, Seung-Jun Bae, Hyun-Jin Kim, Ji-Hoon Lim, Se-Mi Yang, Ok-Joo Park, Dae Hyun Kim, Young-wook Jang, Suk-Won Hwang, Min-Sang Park, Hyun-Kyu Lee, Kwang-II Park, Gil-Shin Moon, Woojin Lee, Mi-Jin Lee, Young-Hyun Jun, Ho-Kyung Lee, Jeong-Don Ihm, Kyung-Ho Kim, Jinyong Choi, Young-Wook Kim
Publikováno v:
ISSCC
A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21 ps and voltage fluctuation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae6ad4b6bd11d5bc9409a494a50f5844
https://doi.org/10.1109/isscc.2007.373509
https://doi.org/10.1109/isscc.2007.373509