Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Saleh Karman"'
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 68:989-997
This paper analyses the noise performances of coupled phase-locked loops, providing closed-form expressions for the transfer functions of the various noise sources, and presents a novel coupling topology, whose goal is the reduction of both in-band a
Autor:
Alessio Santiccioli, Salvatore Levantino, Francesco Tesolin, Michael Peter Kennedy, Angelo Parisi, Andrea L. Lacaita, Abanob Shehata, Luca Avallone, Luca Bertulessi, Simone M. Dartizio, Saleh Karman, Francesco Buccoleri, Carlo Samori, Mario Mercandelli
Publikováno v:
ISSCC
The advent of the next-generation wireless communication standards demands increasingly faster transceivers, posing extremely challenging requirements on the frequency-synthesizer integrated jitter [1, 2]. As demonstrated in [1], the bang-bang digita
Autor:
Angelo Parisi, Alessio Santiccioli, Francesco Tesolin, Saleh Karman, Luca Avallone, Simone M. Dartizio, Andrea L. Lacaita, Abanob Shehata, Mario Mercandelli, Michael Peter Kennedy, Luca Bertulessi, Salvatore Levantino, Francesco Buccoleri, Carlo Samori
This work introduces a bang-bang fractional-N phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1beefc40ae39364ae98ece7def353ed0
http://hdl.handle.net/11311/1187540
http://hdl.handle.net/11311/1187540
Autor:
Salvatore Levantino, Mario Mercandelli, Alessandro Dago, Carlo Samori, Francesco Tesolin, Saleh Karman
This work presents a novel architecture of frequency synthesizer which allows to easily couple two digital PLLs (synchronized to the same reference source) and scale phase noise and power consumption. The second-harmonic component of the two digital
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::03a1e1eb4ae3eb1edb1de60ee5f41447
http://hdl.handle.net/11311/1183865
http://hdl.handle.net/11311/1183865
This paper analyzes the absolute jitter performance of digital phase-locked loops and compares the case when either a multi-bit time-to-digital converter with mid-rise characteristic or a bang-bang phase detector is adopted. The linear equivalent mod
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e162f92f17d00ebf945f8c98cd1e5c14
http://hdl.handle.net/11311/1141862
http://hdl.handle.net/11311/1141862
Autor:
Alessandro Garghetti, Salvatore Levantino, Luca Bertulessi, Luigi Grimaldi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Saleh Karman
Publikováno v:
ISSCC
Digital phase-locked loops (DPLLs) have been demonstrated to achieve excellent performance as fractional-N frequency synthesizers in the sub-6GHz range, but, when used in the mm-wave range, at 30GHz and above, they typically feature poor jitter-power
Autor:
Salvatore Levantino, Luca Bertulessi, Saleh Karman, Andrea L. Lacaita, Carlo Samori, Dmytro Cherniak, Alessandro Garghetti
This article describes the implementation of a 30-GHz frequency synthesizer. The target is to reduce the gap in terms of jitter-power product that exists between millimeter-wave and RF synthesizers, using a low-cost 65-nm LP CMOS technology. The circ
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::332e72d4b315bea15fc14261814e3000
http://hdl.handle.net/11311/1112489
http://hdl.handle.net/11311/1112489