Zobrazeno 1 - 10
of 34
pro vyhledávání: '"Sakurako Natori"'
Autor:
Masatoshi Yamato, Kenichi Oyama, Arisa Hara, Sakurako Natori, Hidetami Yaegashi, Kyohei Koike, Shouhei Yamauchi, Kazuki Yamada
Publikováno v:
SPIE Proceedings.
Lithographic scaling continues to advance by extending the life of 193nm immersion technology, and spacer-type multi-patterning is undeniably the driving force behind this trend. Multi-patterning techniques such as self-aligned double patterning (SAD
Autor:
Kenichi Oyama, Mark John Maslow, Masatoshi Yamato, Paolo Di Lorenzo, Carlos Fonseca, Kyohei Koike, Shohei Yamauchi, Hidetami Yaegashi, Vadim Timoshkov, Arisa Hara, Sakurako Natori, Ton Kiers
Publikováno v:
SPIE Proceedings.
Multi-patterning has been adopted widely in high volume manufacturing as 193 immersion extension, and it becomes realistic solution of nano-order scaling. In fact, it must be key technology on single directional (1D) layout design [1] for logic devis
Autor:
Sakurako Natori, Kenichi Oyama, Kyohei Koike, Arisa Hara, Hidetami Yaegashi, Shohei Yamauchi, Masatoshi Yamato
Publikováno v:
SPIE Proceedings.
Gridded design rules[1] is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line and space pattern by using multiple patterning techniques such as self-aligned multip
Autor:
Masatoshi Yamato, Kenichi Oyama, Arisa Hara, Shohei Yamauchi, Hidetami Yaegashi, Sakurako Natori
Publikováno v:
ECS Transactions. 60:273-278
The double patterning process has become a technology for extending the life of 193-nm immersion lithography. It is the most useful techniques of advancing downscaling in semiconductors and can theoretically be used scale infinitely down. For the sel
Autor:
Shoichi Yamauchi, Arisa Hara, Hidetami Yaegashi, Masatoshi Yamato, Sakurako Natori, Kenichi Oyama
Publikováno v:
Journal of Photopolymer Science and Technology. 27:731-738
Autor:
Masatoshi Yamato, Shoichi Yamauchi, Arisa Hara, Hidetami Yaegashi, Kenichi Oyama, Sakurako Natori
Publikováno v:
Journal of Photopolymer Science and Technology. 27:491-496
Autor:
Arisa Hara, Masatoshi Yamato, Kenichi Oyama, Hidetami Yaegashi, Sakurako Natori, Shohei Yamauchi
Publikováno v:
ECS Transactions. 52:281-286
Double Pattering process is one of the most promising lithography techniques for sub-40nm half-pitch technology node. Especially, Self-aligned spacer Double Patterning (SADP) has been adopted in HVM of NAND FLASH memory device[1], and it is expanding
Autor:
Hidetami Yaegashi, Kyohei Koike, Masatoshi Yamato, Kenichi Oyama, Sakurako Natori, Shohei Yamauchi, Arisa Hara
Publikováno v:
SPIE Proceedings.
Gridded design rules[1] is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line and space pattern by using multiple patterning techniques such as self-aligned multip
Autor:
Sakurako Natori, Kenichi Oyama, Shohei Yamauchi, Masatoshi Yamato, Hidetami Yaegashi, Kyohei Koike, Arisa Hara
Publikováno v:
SPIE Proceedings.
One of the practical candidates to produce 7nm node logic devices is to use the multiple patterning with 193-immersion exposure. For the multiple patterning, it is important to evaluate the relation between the number of mask layer and the minimum pi
Autor:
Masatoshi Yamato, Arisa Hara, Kyohei Koike, Shohei Yamauchi, Kenichi Oyama, Hidetami Yaegashi, Sakurako Natori
Publikováno v:
SPIE Proceedings.
The continuously scaling of complex device geometries is driving by the self-aligned multiple patterning techniques. Depending on such simplified LS scaling, FinFET design rule has been accelerated to unidirectional design layout. [1] In particular F