Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Sajjad Parvin"'
Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates
Autor:
Sajjad Parvin, Mustafa Altun
Publikováno v:
IEEE Access, Vol 7, Pp 163939-163947 (2019)
Reversible logic has 100% fault observability meaning that a fault in any circuit node propagates to the output stage. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible logic
Externí odkaz:
https://doaj.org/article/da0132143495418cbd0413defc726344
Publikováno v:
IEEE Access, Vol 6, Pp 74475-74484 (2018)
Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes always result in an error at the output. This is a unique feature for online or concurrent fault tolerance and the main mo
Externí odkaz:
https://doaj.org/article/13faa514bfd84d3aa565c61359da605d
Publikováno v:
Proceedings of the 28th Asia and South Pacific Design Automation Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a17df63f027465d89d8a969159d8edef
https://doi.org/10.1145/3566097.3567919
https://doi.org/10.1145/3566097.3567919
Autor:
Mustafa Altun, Sajjad Parvin
Publikováno v:
ISVLSI
This paper presents hardware-aware training techniques for efficient hardware implementation of feedforward artificial neural networks (ANNs). Firstly, an investigation is done on the effect of the weight initialization on the hardware implementation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0008349cb208fdd06707a143365ad0ec
https://doi.org/10.1109/isvlsi51109.2021.00080
https://doi.org/10.1109/isvlsi51109.2021.00080
Publikováno v:
ISVLSI
In this paper, we propose an efficient method to realize a convolution layer of the convolution neural networks (CNNs). Inspired by the fully-connected neural network architecture, we introduce an efficient computation approach to implement convoluti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::767ea2d22f2fb655d71d0fc32fd08ded
https://aperta.ulakbim.gov.tr/record/234352
https://aperta.ulakbim.gov.tr/record/234352
Publikováno v:
IEEE Access, Vol 6, Pp 74475-74484 (2018)
Unlike conventional CMOS circuits, reversible circuits do not have latent faults, so faults occurring in internal circuit nodes always result in an error at the output. This is a unique feature for online or concurrent fault tolerance and the main mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::feea4a1e0419dd9f65ab32907411a082
https://ieeexplore.ieee.org/document/8554085/
https://ieeexplore.ieee.org/document/8554085/
Autor:
Mustafa Altun, Sajjad Parvin
Publikováno v:
IOLTS
In reversible circuits, a fault as a change in logic value at a circuit node always alters an output logic value, so observability of faults at the output is 100%. In other words, reversible circuits are latent-fault-free. Our motivation is to incorp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa563fbe23a47f8580c862d515b7d419
https://doi.org/10.1109/iolts.2019.8854440
https://doi.org/10.1109/iolts.2019.8854440
Autor:
Aidin Tofangdarzade, Sajjad Parvin
Publikováno v:
2017 Iranian Conference on Electrical Engineering (ICEE).
In this paper, a novel analytical approach is proposed for phase noise of 4-stages multi path ring oscillators. The method utilizes the Generalized Adler's equation to describe the locking dynamics and assumes the noise as a small signal perturbation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d85fe916165156116f24ed5ec503b1fc
https://doi.org/10.1109/iraniancee.2017.7985097
https://doi.org/10.1109/iraniancee.2017.7985097