Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Sailesh Kottapalli"'
Autor:
M. Arafa, Bob Valentine, Sujal Vora, Sailesh Kottapalli, Ian M. Steiner, Andy Rudoff, Sreenivas Mandava, Akhilesh Kumar, Geetha Vedaraman, Bahaa Fahim, Lily Pao Looi
Publikováno v:
IEEE Micro. 39:29-36
This paper introduces advances in the performance of AI and deep learning inference application on the next generation Intel Xeon Scalable processor, code-named Cascade Lake, which also includes support for Intel Optane DC persistent memory, a breakt
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::15d126691e872de6d9c0386acfda2a5a
https://doi.org/10.1109/mm.2019.2899330
https://doi.org/10.1109/mm.2019.2899330
Autor:
Jeff Baxter, Geetha Vedaraman, Irma Esmer Papazian, Brian S. Morris, Jeffrey D. Chamberlain, Sailesh Kottapalli
Publikováno v:
IEEE Micro. 35:16-25
The Intel microarchitecture code named Ivy Bridge (IVB) represents Intel's first processor (CPU) design that services product markets from high-end desktops to mission-critical computing. With one converged design, IVB enables a rich portfolio of pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87d054fedd51a9d94ee186e67cfdd194
https://doi.org/10.1109/mm.2015.33
https://doi.org/10.1109/mm.2015.33
Autor:
Sailesh Kottapalli, Sujal Vora, Stefan Rusu, Matt Ratta, Raj Varada, Harry Muljono, J. Stinson, J. Chang, Simon M. Tam, David J. Ayers
Publikováno v:
ISSCC
This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::131466a8ef50023a6828f6c914c22b7c
https://doi.org/10.1109/jssc.2009.2034076
https://doi.org/10.1109/jssc.2009.2034076
Autor:
Irma Esmer, Sailesh Kottapalli
Publikováno v:
Hot Chips Symposium
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12af3bcd2e958a6c90e6383c2d37272b
https://doi.org/10.1109/hotchips.2014.7478833
https://doi.org/10.1109/hotchips.2014.7478833
Autor:
Dheemanth Nagaraj, Sailesh Kottapalli
Publikováno v:
2010 IEEE Hot Chips 22 Symposium (HCS).
This article consists of a collection of slides from the author's conference presentation on Intel's Westmere-EX, a 20 thread server CPU family of products. Some of the specific topics discussed include: the special features, system specifications, a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ca7d17400ecc4a83465b505c22198a4
https://doi.org/10.1109/hotchips.2010.7480083
https://doi.org/10.1109/hotchips.2010.7480083
Autor:
Stefan Rusu, J. Stinson, Sailesh Kottapalli, David J. Ayers, Matt Ratta, Simon M. Tam, Raj Varada, Sujal Vora, J. Chang, Harry Muljono
Publikováno v:
ESSCIRC
This paper presents the power reduction and management techniques for the 45nm, 8-core Nehalem-EX processor. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leaka
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ec3671abd2362cfa846aed02e206c3b
https://doi.org/10.1109/esscirc.2009.5326028
https://doi.org/10.1109/esscirc.2009.5326028
Autor:
Sailesh Kottapalli, Jeff Baxter
Publikováno v:
2009 IEEE Hot Chips 21 Symposium (HCS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ff025b08a1bf7d6b342468955615aebb
https://doi.org/10.1109/hotchips.2009.7478350
https://doi.org/10.1109/hotchips.2009.7478350