Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Sagar P Karalkar"'
Publikováno v:
2021 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81bb04314fdf45f257dfdef235719a44
https://doi.org/10.1109/ipfa53173.2021.9617387
https://doi.org/10.1109/ipfa53173.2021.9617387
Publikováno v:
IRPS
An effective design for medium voltage ESD nMOS power clamp with layout modification of the source junction in 28nm high voltage CMOS technology is presented. Modification of N+/P+ source segmented design of ESD nMOS shows the most efficient ESD powe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c1dbcd3814971ed5f8c7eb2be5d8a90
https://doi.org/10.1109/irps46558.2021.9405206
https://doi.org/10.1109/irps46558.2021.9405206
Autor:
Vishal Ganesan, Tom Herrmann, Sagar P Karalkar, Kyongjin Hwang, Bhoopendra Singh, Sevashanmugam Marimuthu, Robert Gauthier, Alban Zaka
Publikováno v:
IRPS
An effective design for self-protection medium voltage nMOS with modification of drain junction in 28nm high voltage CMOS technology is presented. Pull down nMOS of the output driver is the main electrostatic discharge path. Design of Source/Drain ju
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0bffd0b13d89fdb179c1443b8cf42e25
https://doi.org/10.1109/irps45951.2020.9129515
https://doi.org/10.1109/irps45951.2020.9129515