Výsledky vyhledávání - "Sadayuki Ohnishi"

Accurate Modeling Method for Cu Interconnect

Autor: Hiroyasu Minda, Michio Sakurai, Sadayuki Ohnishi, Hideo Sakamoto, Noriaki Oda, Kenta Yamada, Norio Okada, Manabu Iguchi, Hiroshi Kitahara, Makoto Yasuda, Toshiyuki Takewaki, Masayuki Hiroi, Yoshihiko Asai, M. Suzuki

Publikováno v: IEICE Transactions on Electronics. :968-977

This paper proposes an accurate modeling method of the copper interconnect cross-section in which the width and thickness dependence on layout patterns and density caused by processes (CMP, etching, sputtering, lithography, and so on) are fully, inco

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::54a4aba4c31095d4edb34ea17f2f5fd5
https://doi.org/10.1093/ietele/e91-c.6.968

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Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation

Autor: Noriaki Oda, Sadayuki Ohnishi, Kenta Yamada, Kazuyoshi Ueno, Y. Kakuhara, Masayoshi Tagami, Shuji Sone, Hiroyuki Kunishima, Yoshihiro Hayashi, Hironori Imura, M. Sekine, Naoyoshi Kawahara

Publikováno v: IEICE Transactions on Electronics. :848-855

A novel interconnect design concept named "ASIS (Appilication-specific Interconnect Structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power, or

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::a289d5e5d9d207328955c1f3ec8bc99d
https://doi.org/10.1093/ietele/e90-c.4.848

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Chip-level performance maximization using ASIS (application-specific interconnect structure) wiring design concept for 45 nm CMOS devices

Autor: Kenta Yamada, M. Sekine, Noriaki Oda, Naoyoshi Kawahara, H. Imura, Y. Kakuhara, Kazuyoshi Ueno, Hiroyuki Kunishima, Sadayuki Ohnishi, M. Tagami, Yoshihiro Hayashi, S. Sone

Publikováno v: IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

A novel interconnect design concept named "ASIS (application-specific interconnect structure)" is presented for 45 nm CMOS performance maximization. Basic scheme of ASIS is that corresponding to applications, such as high-performance, low-power or hi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f64acd895cc8cdefbace582d1fa4f36c
https://doi.org/10.1109/iedm.2005.1609538

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