Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Sachin Satish Idgunji"'
Autor:
Mark Charlebois, Dave Fick, Sachin Satish Idgunji, Yuchen Zhou, Michael Thomson, Ashish Sirasao, George Yuan, Anton Lokhmotov, Koichi Yamada, Tom St. John, Bing Yu, Jeff Jiao, Arun Tejusve Raghunath Rajan, Paulius Micikevicius, Ephrem C. Wu, Francisco Massa, Carole-Jean Wu, Hanlin Tang, David Lee, William Chou, Frank Wei, Jared Duke, Cody Coleman, Sam Davis, Jeffery Liao, Itay Hubara, Dilip Sequeira, Lingjie Xu, Pan Deng, Vijay Janapa Reddi, Guenther Schmuelling, Gennady Pekhimenko, Maximilien Breughe, Peng Meng, Greg Diamos, David Kanter, Colin Osborne, Thomas B. Jablin, Peizhao Zhang, Fei Sun, Pankaj Kanwar, Ramesh Chukka, J. Scott Gardner, Aaron Zhong, Christine Cheng, Peter Mattson, Brian M. Anderson
Publikováno v:
ISCA
Machine-learning (ML) hardware and software system demand is burgeoning. Driven by ML applications, the number of different ML inference systems has exploded. Over 100 organizations are building ML inference chips, and the systems that incorporate ex
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7a2417894de20d08d29ba667a4080f9a
Publikováno v:
MICRO
In upcoming architectures that stack processor and DRAM dies, temperatures are higher because of the increased transistor density and the high inter-layer thermal resistance. However, past research has underestimated the extent of the thermal bottlen
Autor:
Almutaz Adileh, Stavros Volos, Djordje Jevdjic, Michael Ferdman, Emre Ozer, Sachin Satish Idgunji, Javier Picorel, Babak Falsafi, Onur Kocberber, Boris Grot, Pejman Lotfi-Kamran
Publikováno v:
ISCA
Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommoda
Publikováno v:
Journal of Low Power Electronics. 4:48-59
Low Power techniques such as multi-voltage islands, voltage scaling and power gating are gaining acceptance to address the need for managing energy and power during run time as well as during standby modes. These design techniques increase the comple
Autor:
Sachin Satish Idgunji, Tezaswi Raja, Daniel Lin, Aniket Naik, Xin Chang, Sunil Sudhakaran, Yaping Zhou
Publikováno v:
2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems.
Power noise aware clocking in modern chips can reduce power supply noises and relax on-chip timing requirements during power drooping. This paper proposes and demonstrates a power noise simulation method to consider these two effects. Measurement res
Autor:
Cezary Pietrzyk, Greg Yeric, Imran Iqbal, Robert Campbell Aitken, Sachin Satish Idgunji, Vikas Chandra
Publikováno v:
2010 International Conference on Microelectronic Test Structures (ICMTS).
We present a test chip architecture which embeds a thorough set of process characterization ring oscillators into a synthesized digital circuit, such as a processor core. We discuss the motivation, implementation, and results from sub-40nm technology