Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Sabbir A. Osmany"'
Publikováno v:
Analog Integrated Circuits and Signal Processing. 74:545-556
This paper analyses substrate-related spurious tones in fractional-N phase-locked loops with integrated VCOs. Spur positions are calculated and experimentally verified as a function of the divider ratios of prescaler and programmable divider. For an
Publikováno v:
Analog Integrated Circuits and Signal Processing. 67:319-330
An integrated phase-locked loop (PLL) with low phase noise is presented, which is robust with respect to variations of device parameters with process, supply voltage, and temperature (PVT). The low-noise CMOS voltage-controlled oscillator (VCO) emplo
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 57:1914-1924
We present an analytical frequency-domain phase-noise model for fractional-N phase-locked loops (PLLs). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charg
Publikováno v:
Advances in Radio Science, Vol 5, Pp 313-320 (2007)
We present an analytical phase noise model for fractional-N phase-locked loops (PLL) with emphasis on integrated RF synthesizers in the GHz range. The noise of the crystal reference, the voltage-controlled oscillator (VCO), the loop filter, the charg
Publikováno v:
2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.
We present an integrated fractional-N frequency synthesizer providing in-phase / quadrature phase signal over the frequency bands 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and in-phase signal over 20–28 GHz for software-defined radio applications. The
Publikováno v:
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF).
We present an integrated fractional-N frequency synthesizer providing in-phase / quadrature phase signal over the frequency bands 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and in-phase signal over 20–28 GHz for software-defined radio applications. An
Publikováno v:
2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting.
We present an integrated frequency synthesizer which is able to provide in-phase / quadrature phase signal over the frequency bands 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and in-phase signal over 20–28 GHz for software-defined radio applications. F
Autor:
Rudiger Follmann, Sabbir A. Osmany, Frank Herzel, Heinz-Volker Heyer, Klaus Schmalz, Thomas Podrebersek, J. Christoph Scheytt, Wolfgang Winkler
Publikováno v:
2009 IEEE Radio Frequency Integrated Circuits Symposium.
We present a single-chip fractional-N PLL for space applications. The design employs a high-current charge pump with optimum output biasing and a low-current charge pump for extension of the tuning range. We show that the extension of the tuning rang
Autor:
Thomas Podrebersek, U. Jagdhold, Klaus Schmalz, M. Engels, V. Heyer, D. Kother, Rudiger Follmann, Sabbir A. Osmany, Wolfgang Winkler, T. Kohl, Frank Herzel
Publikováno v:
2008 IEEE MTT-S International Microwave Symposium Digest.
Broad band satellite communication makes high demands on linear low phase noise signals. One example is HDTV. For this application converters are required (e.g. from 30 GHz to 20 GHz), which themselves require very low phase noise programmable synthe
Autor:
Frank Herzel, M. Engels, J.C. Scheytt, Sabbir A. Osmany, Klaus Schmalz, Wolfgang Winkler, Srdjan Glisic
Publikováno v:
2008 IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems.
We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 mum SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel char