Zobrazeno 1 - 10
of 30
pro vyhledávání: '"S.S. Batth"'
Publikováno v:
Computer Networks. 53:596-612
Detection of multiple timing faults is a challenging task because these faults, although may be detectable individually, can mask each other's faulty behavior, making a faulty implementation under test (IUT) indistinguishable from a non-faulty one du
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::350eed218a39c968bceb575b37420626
https://doi.org/10.1016/j.comnet.2008.10.025
https://doi.org/10.1016/j.comnet.2008.10.025
Publikováno v:
IEEE Transactions on Instrumentation and Measurement. 57:1102-1111
Inherent timing variables and constraints in communication protocols require new extended finite-state machine (EFSM) models to formally represent their behavior, particularly for test generation purposes. However, infeasible paths due to the conflic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::239fa01a8a8d53d87a32d57b0013794a
https://doi.org/10.1109/tim.2007.915145
https://doi.org/10.1109/tim.2007.915145
Publikováno v:
IEEE Transactions on Computers. 57:274-288
A set of graph augmentation algorithms is introduced to model a class of timing faults in timed-EFSM models. It is shown that the test sequences generated based on our models can detect 1 -clock and n-clock timing faults and incorrect timer setting f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50519992af1dc31c5203b00ddba228b0
https://doi.org/10.1109/tc.2007.70772
https://doi.org/10.1109/tc.2007.70772
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540731955
FORTE
FORTE
In this paper, we apply our timing fault modeling strategy to writing formal specifications for communication protocols. Using the formal language of Specification and Description Language (SDL), we specify the Controller process of rail-road crossin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd70d17af8a9ec0707f9e1a6aeed5a8b
https://doi.org/10.1007/978-3-540-73196-2_4
https://doi.org/10.1007/978-3-540-73196-2_4
Publikováno v:
2006 IEEE Instrumentation and Measurement Technology Conference Proceedings.
An implementation under test (IUT) can be formally described using finite-state machines (FSMs). Due to the presence of inherent timing constraints and variables in a communication protocol, an IUT is modeled more accurately by using extended finite-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8083e546af7d80e827584d62b1a4aeff
https://doi.org/10.1109/imtc.2006.328260
https://doi.org/10.1109/imtc.2006.328260
Publikováno v:
2005 IEEE Instrumentationand Measurement Technology Conference Proceedings.
The classification and detection of single timing faults in timed FSMs are introduced. A graph augmentation method is used to formulate the detection models for timing faults. It is shown that, by using our graph augmentation models, a faulty IUT end
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::818ac5375e0fc90afa8678ec3a2e5d9c
https://doi.org/10.1109/imtc.2005.1604598
https://doi.org/10.1109/imtc.2005.1604598
Publikováno v:
SIIT
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9e54efea3e843b509c0918fda8d44c5
https://doi.org/10.1109/siit.2005.1563811
https://doi.org/10.1109/siit.2005.1563811
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783540260547
TestCom
TestCom
Multiple timing faults, although detectable individually, can hide each other’s faulty behavior making the faulty system indistinguishable from a non-faulty one. A set of graph augmentations are introduced for single timing faults. The fault detect
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f0ee78801f4958ac2a6a122023de795
https://doi.org/10.1007/11430230_14
https://doi.org/10.1007/11430230_14
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Akademický článek
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