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pro vyhledávání: '"S.K Aris"'
Autor:
V. B. Naik, K. Yamane, J. H. Lim, T. Y. Lee, J. Kwon, Behin Aein, N. L. Chung, L. Y. Hau, R. Chao, D. Zeng, Y. Otani, C Chiang, Y. Huang, L. Pu, N. Thiyagarajah, S. H. Jang, W. P. Neo, H. Dixit, S.K Aris, L. C. Goh, T. Ling, J. Hwang, J. W. Ting, L. Zhang, R. Low, N. Balasankaran, C. S. Seet, S. Ong, J. Wong, Y. S. You, S. T. Woo, S. Y. Siah
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
We report a reliable TDDB lifetime projection model using power law verified from 40Mb STT-MRAM macro at sub-ppm failure rate to realize nearly unlimited endurance for cache applications. A specially designed macro, having internal temperature contro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b950a86848127f4ffc230063ff57e42d
https://doi.org/10.1109/vlsitechnology18217.2020.9265086
https://doi.org/10.1109/vlsitechnology18217.2020.9265086
