Zobrazeno 1 - 10
of 113
pro vyhledávání: '"S.A. Bota"'
Publikováno v:
Microelectronics Reliability. 65:280-288
Increased process variability and reliability issues present a major challenge for future SRAM trends. Non-intrusive and accurate SRAM stability measurement is crucial for estimating yield in large SRAM arrays. Conventional SRAM variability metrics r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f25e7d2b67b71dee297d8657e621687
https://doi.org/10.1016/j.microrel.2016.07.154
https://doi.org/10.1016/j.microrel.2016.07.154
Publikováno v:
Microelectronics Reliability. 54:2613-2620
We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-li
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f46afb3cc9365bde1583aa4d4d65db85
https://doi.org/10.1016/j.microrel.2014.05.009
https://doi.org/10.1016/j.microrel.2014.05.009
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 22:1557-1569
We report and analyze the dependence of complex gates delay with the sensitization vector and its variation-that gets up to 40% in 65-nm CMOS technologies-and include its effect in the path delay estimation-that can be in the order of 16%. The gate d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87450c1ad3e2f3a336d28380f287a849
https://doi.org/10.1109/tvlsi.2013.2276738
https://doi.org/10.1109/tvlsi.2013.2276738
Publikováno v:
Microelectronics Reliability. 52:2799-2804
Resistive bridges are a major class of defects in nanometer technologies that can escape test, posing a serious reliability risk for CMOS IC circuits. The increase of process parameter variations represents a challenge for resistive bridge detection
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e6c4e881acaa4f446ba583bd4c40b2b1
https://doi.org/10.1016/j.microrel.2012.04.001
https://doi.org/10.1016/j.microrel.2012.04.001
Publikováno v:
Microelectronics Reliability. 51:350-359
We analyze and compare the impact of radiation-induced transient effects based on evaluating the critical charge parameter for 6T and 8T SRAMs during hold, read and write operations. Results on a commercial 65 nm CMOS technology show that 6T and 8T c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2457bde684b237e392c70b85de6e6ba
https://doi.org/10.1016/j.microrel.2010.09.002
https://doi.org/10.1016/j.microrel.2010.09.002
Publikováno v:
IEEE Transactions on Nuclear Science. 58:177-186
In this paper we discuss the noise analysis of time variant shapers in the frequency domain, based on well established concepts of the theory of time varying circuits. A frequency domain extension of the techniques typically adopted for noise analysi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb8dcb2f6c184882c0218b3e37c4474b
https://doi.org/10.1109/tns.2010.2101082
https://doi.org/10.1109/tns.2010.2101082
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. 57:280-284
Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the tra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6971b5b325a2cb00be06b84f12c03938
https://doi.org/10.1109/tcsii.2010.2043462
https://doi.org/10.1109/tcsii.2010.2043462
Publikováno v:
IEICE Electronics Express. 5:1042-1048
A chaotic integrated circuit is designed and fabricated using a 0.35µm CMOS process. The circuit iterates an N-shaped transfer function using a small analog neural network. One of the advantages of the proposed circuit is its small circuit area with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e2ba58aa604df8d259711e1cc866ea0
https://doi.org/10.1587/elex.5.1042
https://doi.org/10.1587/elex.5.1042
Publikováno v:
IEEE Design & Test of Computers. 23:414-424
In this article, we analyze the impact of within-die thermal gradients on clock skew, considering temperature's effect on active devices and the interconnect system. This effect, along with the fact that the test-induced thermal map can differ from t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d394cefffae721b0c8b197d053821c3
https://doi.org/10.1109/mdt.2006.126
https://doi.org/10.1109/mdt.2006.126
Autor:
Lluis Garrido, Jordi Riera, Ricardo Graciani, A. Comerma, David Gascon, X. Cano, A. Herms, S.A. Bota
Publikováno v:
Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment. 551:458-468
The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0a86bfb04ff58e3ad437987f8ef1f42c
https://doi.org/10.1016/j.nima.2005.06.043
https://doi.org/10.1016/j.nima.2005.06.043