Zobrazeno 1 - 10
of 30
pro vyhledávání: '"S.A. Al-Arian"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8:534-541
In this paper, we present an algorithm for partitioning sequential circuits. This algorithm is based on an analysis of a circuit's primary input cones and fanout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasi
Publikováno v:
Computers & Electrical Engineering. 23:319-328
Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has dramatically increased. Testing such circuits is becoming a severe problem. With the increased densities of integrated circuits, several different types of
Publikováno v:
IEEE Design & Test of Computers. 10:68-79
Procedure 5012 of Mil-Std-883, which describes requirements for the logic model, the assumed fault model and universe, fault classing, fault simulation and reporting of test results for digital microcircuits is described. The procedure provides a con
Publikováno v:
Great Lakes Symposium on VLSI
A new sequential circuit partitioning algorithm is introduced which enhances pseudo-exhaustive testing. Our PIFAN algorithm is based on an analysis of Primary Input cones and FANout values. Results are presented which show that PIFAN offers significa
Autor:
S.A. Al-Arian
Publikováno v:
ITC
It is argued that a broad-based VLSI curriculum should be established in the university. In conjunction with theoretical teaching, facilities that include an integrated design and test environment, CAD tools, and ATE (automatic test equipment) should
Autor:
H.Y. Abujbara, S.A. Al-Arian
Publikováno v:
Proceedings. IEEE Energy and Information Technologies in the Southeast'.
GaAs technology is reviewed from a testing-engineer point of view, and the fault behavior of GaAs transistor is examined. Timing faults are shown to be the most serious faults in GaAs. Timing algebra is presented to propagate and detect timing faults
Publikováno v:
IEEE International Symposium on Circuits and Systems.
A description is given of research on a WSI FFT processor. Attention is focused on the design methodology, architecture, and sparing strategy and restructuring. The basic cells utilized are the MSA and the coefficient ROM. The wafer thus has only two
Autor:
H.P. Kunamneni, S.A. Al-Arian
Publikováno v:
Conference Proceedings '88., IEEE Southeastcon.
The VLSI design problem was partitioned to different levels. The authors' objective was to develop an expert system to transform the behavioral descriptions (as given by the user or contractor) to the algorithmic state machine level (where data and c
Autor:
K.A. Kwiat, S.A. Al-Arian
Publikováno v:
ITC
An acceptable standard is developed for relating fault simulator results from different simulators. Each simulator should verify the good circuit and evaluate the effectiveness of the generated test patterns (fault coverage). A hypothetical standard
Autor:
S.A. Al-Arian, M.A. Al-Kharji
Publikováno v:
ICCD
Novel techniques and procedures for choosing a sample from the entire fault population are presented. The fault coverage evaluation of the sample and the fault population, given a random test set, are evaluated and proved to be equal, or within a sam