High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

Autor: E. Engbrecht, Edward P. Maciejewski, Christopher D. Sheraw, R. Divakaruni, Zhengwen Li, Allen H. Gabor, L. Economikos, Fernando Guarin, N. Zhan, H-K Lee, MaryJane Brodsky, Kenneth J. Stein, Siyuranga O. Koswatta, Y. Yang, Byeong Y. Kim, J. Hong, A. Bryant, Herbert L. Ho, Ruqiang Bao, Nicolas Breil, Babar A. Khan, E. Woodard, W-H. Lee, C-H. Lin, A. Levesque, Kevin McStay, V. Basker, Viraj Y. Sardesai, C. Tran, A. Ogino, Reinaldo A. Vega, C. DeWan, Shreesh Narasimha, J-J. An, Amit Kumar, A. Aiyar, Ravikumar Ramachandran, W. Wang, X. Wang, W. Nicoll, D. Hoyos, A. Friedman, Barry Linder, Yongan Xu, E. Alptekin, Cathryn Christiansen, S. Polvino, Han Wang, Scott R. Stiffler, G. Northrop, S. Saudari, J. Rice, Saraf Iqbal Rashid, Sunfei Fang, Michael V. Aquilino, Z. Ren, B. Kannan, Geng Wang, Noah Zamdmer, T. Kwon, Paul D. Agnello, Hasan M. Nayfeh, S. Jain, Robert R. Robison, M. Hasanuzzaman, J. Cai, L. Lanzerotti, D. Wehelle-Gamage, Basanth Jagannathan, J. Johnson, E. Kaste, Kai Zhao, Huiling Shang, Carl J. Radens, Shariq Siddiqui, Y. Ke, D. Ferrer, Ximeng Guan, D. Conklin, K. Boyd, K. Henson, Siddarth A. Krishnan, Bernard A. Engel, H. Dong, S. Mahajan, Unoh Kwon, Dominic J. Schepis, William Y. Chang, Liyang Song, Brian J. Greene, Chengwen Pei, S.-J. Jeng, Clevenger Leigh Anne H, Vijay Narayanan, C. Zhu, Wai-kin Li, Henry K. Utomo, Wei Liu, Dureseti Chidambarrao

Publikováno v: 2014 IEEE International Electron Devices Meeting.

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generat

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6233530b0b3fd6ddc14276a018716523
https://doi.org/10.1109/iedm.2014.7046977

Si-Ge heterojunction bipolar technology for high-speed integrated circuits

Autor: J. Malinowski, D. Sunderland, D. C. Ahlgren, David Harame, M. Soyuer, S.-J. Jeng, Kathryn T. Schonenberg, D. Nguyen-Ngoc, K. Stein, M. Gilbert, B. Meyerson

Publikováno v: Canadian Journal of Physics. 74:159-166

This review discusses the fundamentals of SiGe epitaxial base heterojunction bipolar transistor (HBT) technology that have been developed for use in analog and mixed-signal applications in the 1–20 GHz range. The basic principles of operation of th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::0315989fd14894e814004aa3c54e133f
https://doi.org/10.1139/p96-851

Self-aligned SiGe NPN transistors with 285 GHz f/sub MAX/ and 207 GHz f/sub T/ in a manufacturable technology

Autor: Andreas D. Stricker, Peter Andrew Smith, Jae-Sung Rieh, John E. Florkey, S.-J. Jeng, H. Chen, Marwan H. Khater, Gregory G. Freeman, J. Johnson, Kathryn T. Schonenberg, David C. Ahlgren, E. Mengistu, Basanth Jagannathan, S. Subbanna, C.M. Schnabel, David R. Greenberg, F. Golan, Kenneth J. Stein, Francois Pagette, R.A. Groves, David Angell

Publikováno v: IEEE Electron Device Letters. 23:258-260

This paper reports on SiGe NPN HBTs with unity gain cutoff frequency (f/sub T/) of 207 GHz and an f/sub MAX/ extrapolated from Mason's unilateral gain of 285 GHz. f/sub MAX/ extrapolated from maximum available gain is 194 GHz. Transistors sized 0.12/

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::baa60a555d8c26bf4d785edc577ace87
https://doi.org/10.1109/55.998869

High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography

Autor: P. Agnello, T. Ivers, C. Warm, R. Wise, R. Wachnik, D. Schepis, S. Sankaran, J. Norum, S. Luning, Y. Li, M. Khare, A. Grill, D. Edelstein, X. Chen, D. Brown, R. Augur, S. Wu, J. Yu, R.C. Wong, J. Werking, D. Wehella-Gamage, A. Vayshenker, H. Van Meer, R. Van Den Nieuwenhuizen, C. Tian, K. Tabakman, C.Y. Sung, T. Standaert, A. Simon, J. Sim, C. Sheraw, D. Restaino, W. Rausch, R. Pal, C. Prindle, X. Ouyang, C. Ouyang, V. Ontalus, K. Nummy, D. Nielsen, L. Nicholson, A. McKnight, N. Lustig, X. Liu, M.H. Lee, D. Lea, G. Larosa, W. Landers, B. Kim, M. Kelling, S.-J. Jeng, J. Holt, M. Hargrove, S. Grunow, S. Greco, S. Gates, A. Frye, P. Fisher, A. Domenicucci, C. Dimitrakopoulos, G. Costrini, A. Chou, J. Cheng, S. Butt, L. Black, M. Belyansky, I. Ahsan, T. Adam, A. Gabor, C.-H.J. Wu, D. Yang, M. Crouse, C. Robinson, D. Corliss, C. Fonseca, J. Johnson, M. Weybright, A. Waite, H.M. Nayfeh, K. Onishi, S. Narasimha

Publikováno v: 2006 International Electron Devices Meeting.

We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniq

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bf10344b83d49f15325667340363c388
https://doi.org/10.1109/iedm.2006.346879

SiGe HBTs for millimeter-wave applications with simultaneously optimized f/sub T/ and f/sub max/ of 300 GHz

Autor: Peter Andrew Smith, J. Johnson, Marwan H. Khater, S.-J. Jeng, David R. Greenberg, Basanth Jagannathan, S. Sweeney, F. Pagette, K. Stein, D. Sanderson, Kathryn T. Schonenberg, Andreas D. Stricker, Gregory G. Freeman, Thomas N. Adam, Anil K. Chinthakindi, Rajendran Krishnasamy, Christopher M. Schnabel, Jae-Sung Rieh, Kunal Vaed, John E. Florkey, T. Yanagisawa, David C. Ahlgren

Publikováno v: 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

Millimeter-wave applications are gaining growing interest in recent times. To meet the challenges for such applications, SiGe HBTs, with simultaneously optimized f/sub T/ and f/sub max/ of >300 GHz, are developed. To the author's knowledge, this is t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::264be74986f22495026f8152443768cb
https://doi.org/10.1109/rfic.2004.1320632