Zobrazeno 1 - 3
of 3
pro vyhledávání: '"S. V. Gompel"'
Autor:
Philippe Leray, N. Jourdan, O. Varela Pedreira, E. Dentoni-Litta, Thomas Witters, Werner Gillijns, Nancy Heylen, L. Ramakers, E. Grieten, Zaid El-Mekki, Gayle Murdoch, V. Vega-Gonzalez, Anne-Laure Charley, Ivan Ciofi, Zsolt Tokei, H. Vats, S. V. Gompel, M. H. van der Veen, L. Halipre, J. Swerts, A. Haider, Bilal Chehab, S. Park, N. Bazzazian, Quoc Toan Le, B. De Wachter, T. Peissker, Harinarayanan Puliyalil, Naoto Horiguchi, Miroslav Cupak, J. Versluijs, G. T. Martinez, Y. Kimura, R. Kim, J. Geypen, J. Uk-Lee, N. Nagesh, D. Montero, L. Rynders, M. Ercken, D. Batuk, K. Croes, Patrick Verdonck, Manoj Jaysankar, Y. Drissi, T. Webers
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a
Autor:
Zaid El-Mekki, F. Schleicher, Frederic Lazzarino, D. Trivkovic, Zsolt Tokei, B. De-Wachter, S. V. Gompel, L. Halipre, E. Vancoille, S. Decoster, G. Muroch, Thomas Witters, L. Dupas, O. Varela-Pereira, B. Briggs, Quoc Toan Le, Harinarayanan Puliyalil, Christopher J. Wilson, Philippe Leray, N. Jourdan, I. Demonie, C. Lorant, Joost Bekaert, Nancy Heylen, Y. Kimura, Rogier Baert, M. H. van der Veen, J. Versluijs, Miroslav Cupak, Patrick Verdonck, K. Croes, Manoj Jaysankar, Anne-Laure Charley, J. Heijlen, J. Uk-Lee, Ivan Ciofi, Y. Drissi, V. Vega-Gonzalez, S. Paolillo, H. Vats, D. Montero, L. Rynders, Els Kesters, M. Ercken, A. Lesniewska, R. Kim, Lieve Teugels, T. Webers
Publikováno v:
2020 IEEE International Electron Devices Meeting (IEDM).
The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with
Autor:
V. Vega-Gonzalez, J. Bekaert, E. Kesters, Q. T. Le, C. Lorant, O. Varela P., L. Teugels, N. Heylen, Z. El-Mekki, M. van der Veen, T. Webers, C. J. Wilson, H. Vats, L. Rynders, M. Cupak, J. Uk-Lee, Y. Drissi, L. Halipre, A.-L. Charley, P. Verdonck, T. Witters, S. V. Gompel, B. Briggs, Y. Kimura, N. Jourdan, I. Ciofi, A. Gupta, A. Contino, G. Boccardi, S. Lariviere, L. Dupas, B. De-Wachter, E. Vancoille, S. Decoster, F. Lazzarino, M Ercken, P. Debacker, R. Kim, D. Trivkovic, K. Croes, P. Leray, L. Dillemans, Y.-F. Chen, Z. Tokei, J. Versluijs, A. Lesniewska, S. Paolillo, R. Baert, H. Puliyalil
Publikováno v:
2019 IEEE International Electron Devices Meeting (IEDM).
The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dim