Zobrazeno 1 - 10
of 18
pro vyhledávání: '"S. Turgis"'
Autor:
S. Turgis, D. Auvergne
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 17:1090-1098
We present in this paper a novel alternative for the internal power-dissipation estimation of CMOS structures. A first order macromodeling is developed, considering full submicronic additional effects such as input slew dependency of short-circuit cu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::20dc2f515a61000e221309075ea76273
https://doi.org/10.1109/43.736183
https://doi.org/10.1109/43.736183
Publikováno v:
Microelectronic Engineering. 39:209-223
Designing in the deep submicronic range implies to manage trade off between speed and power. This paper presents an improved macro model for the delay and power dissipation of CMOS structures. This model is based on a simple but realistic MOS model t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a978c2c33a782f15358458f324b5a3a2
https://doi.org/10.1016/s0167-9317(97)00176-7
https://doi.org/10.1016/s0167-9317(97)00176-7
Publikováno v:
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.
We present the design of a real time parallel processor for classification adapted to image processing. We propose a geometric classification method by stress polytope training, allowing the use of a large number of parameters and ensuring a high dec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5253c911fea41784bfe1b95bbd8cce61
https://doi.org/10.1109/cicc.1994.379737
https://doi.org/10.1109/cicc.1994.379737
Publikováno v:
EDAC-ETC-EUROASIC
Summary form only given. The authors present the design of a real time parallel processor for classification adapted to image processing. They propose a geometric classification method allowing the use of a large number of parameters and ensuring a h
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c077618c7fc91ae1565dae78dc858b50
https://doi.org/10.1109/edtc.1994.326806
https://doi.org/10.1109/edtc.1994.326806
Publikováno v:
Proceedings European Design and Test Conference. ED & TC 97.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9bdbcc26dae17b95a692025627bcd898
https://doi.org/10.1109/edtc.1997.582423
https://doi.org/10.1109/edtc.1997.582423
Publikováno v:
ISLPD: International Symposium on Low Power Design
ISLPD: International Symposium on Low Power Design, Apr 1995, Dana Point, CA, United States. pp.129-134, ⟨10.1145/224081.224104⟩
ISLPD
ISLPD: International Symposium on Low Power Design, Apr 1995, Dana Point, CA, United States. pp.129-134, ⟨10.1145/224081.224104⟩
ISLPD
International audience; For supply voltage standards such as Vdd > V TN + |V TP | short-circuit power dissipation significantly contributes to the total power dissipation in ICs. We propose a new alternative for the estimation of the short-circuit po
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a10e95b8a079985520d4284c7a8b2589
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241153
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00241153
Publikováno v:
Electronics Letters. 32:2070
The authors present an improved macro-model for the delay of CMOS inverters for a submicrometre process. This model includes input-to-output coupling capacitance, short circuit current and input slope effects. Validations are obtained by comparing si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::19c651c9a2ba05686f26a1bca9896b90
https://doi.org/10.1049/el:19961394
https://doi.org/10.1049/el:19961394
Publikováno v:
Proceedings ED&TC European Design and Test Conference.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cbb6eb6343998f0d90309ba6908e2857
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