Zobrazeno 1 - 10
of 11
pro vyhledávání: '"S. S. Paak"'
Autor:
K.-M. Chung, Ju-Heon Kim, Byeong-Hee Kim, J-H Lee, H.-K. Kang, Youngwoo Cho, J. H. Hwang, Eung-joon Lee, Sang-Don Nam, Sung-yup Jung, Kwang-Myeon Park, J.W. Hwang, B. U. Yoon, Sang Hoon Ahn, Seungwook Choi, Rak-Hwan Kim, S. S. Paak, Jong-min Baek, S. Y. Yoo, E. S. Jung, S. H. Park, T.-J. Yim, Jang-ho Kim, Han-mei Choi, J.-H. Ku, T. Oszinda, J. Chang, Nae-In Lee, I S. Kim
Publikováno v:
2015 IEEE International Interconnect Technology Conference and 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM).
CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new pro
Autor:
Deok-Hyung Lee, Rak-Hwan Kim, S.Y. Yoo, Jeonghyun Baek, Jung-A Choi, K.-M. Chung, E. S. Jung, Il-Goo Kim, Ki-Yeol Park, Soon-Moon Jung, Soomin Ahn, Byung-ki Kim, J.H. Hwang, Jihoon Cha, JiYeon Ku, Eun-hong Lee, S. S. Paak, Y. W. Cho, Min-Sang Kim, D. Park, J.S. Yoon, Jae-Hak Kim, T. Matsuda, Hyoji Choi, Hye-Lan Lee, Sungho Park, Jisu Kim, B. U. Yoon, H. K. Kang, Sang-Don Nam, Jun-Bum Lee, Nae-In Lee
Publikováno v:
Publons
CVD-Ru represents a critically important class of materials for BEOL interconnects that provides Cu reflow capability. The results reported here include superior gap-fill performance, a solution for plausible integration issues, and robust EM / TDDB
Autor:
Fransen, Senne, Willems, Kherim, Philipsen, Harold, Verreck, Devin, Van Roy, Willem, Henry, Olivier Y. F., Arreghini, Antonio, Van den bosch, Geert, Furnemont, Arnaud, Rosmeulen, Maarten
Publikováno v:
IEEE Transactions on Electron Devices; May2022, Vol. 69 Issue 5, p2377-2383, 7p
Publikováno v:
Journal of The Electrochemical Society; 2019, Vol. 166 Issue 4, pD137-D143, 7p
Autor:
Clark, R., Tapily, K., Yu, K.-H., Hakamata, T., Consiglio, S., O’Meara, D., Wajda, C., Smith, J., Leusink, G.
Publikováno v:
APL Materials; 2018, Vol. 6 Issue 5, pN.PAG-N.PAG, 12p
Autor:
Kim, R.-H., Kim, B. H., Kim, J. N., Lee, J. J., Baek, J. M., Hwang, J. H., Hwang, J., Chang, J., Yoo, S. Y., Yim, T.-J., Chung, K.-M., Park, K. H., Oszinda, T., Kim, I S., Lee, E. B., Nam, S. D., Jung, S., Cho, Y. W., Choi, H. J., Kim, J. S.
Publikováno v:
2015 IEEE International Interconnect Technology Conference & 2015 IEEE Materials for Advanced Metallization Conference (IITC/MAM); 2015, p1-4, 4p
Publikováno v:
Japanese Journal of Applied Physics; Jul2017, Vol. 56 Issue 7S2, p1-1, 1p
Publikováno v:
IEEE Transactions on Device & Materials Reliability; Jun2007, Vol. 7 Issue 2, p213-214, 2p
Autor:
Kim, R.-H., Kim, B.H., Matsuda, T., Kim, J.N., Baek, J.M., Lee, J.J., Cha, J.O., Hwang, J.H., Yoo, S.Y., Chung, K.-M., Park, K.H., Choi, J.K., Lee, E.B., Nam, S.D., Cho, Y.W., Choi, H.J., Kim, J.S., Jung, S.Y., Lee, D.H., Kim, I.S.
Publikováno v:
2014 IEEE International Electron Devices Meeting; 2014, p00.4-32.2.4, 0p
Autor:
Eitan N. Shauly
Nowadays over 50% of integrated circuits are fabricated at wafer foundries. This book presents a foundry-integrated perspective of the field and is a comprehensive and up-to-date manual designed to serve process, device, layout, and design engineers.