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Autor:
Sumitha George, Vijaykrishnan Narayanan, Hariram Thirucherai Govindarajan, John Sampson, Jagadish B. Kotra, Madhu Mutyam, S. R. Swamy Saranam Chongala, Mahmut Kandemir
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 39:3881-3892
So-called “tagless” caches have become common as a means to deal with the vast L4 last-level caches (LLCs) enabled by increasing device density, emerging memory technologies, and advanced integration capabilities (e.g., 3-D). Tagless schemes ofte