Zobrazeno 1 - 10
of 46
pro vyhledávání: '"S. Matsue"'
Autor:
S. Matsue, H. Makino, H. Nakano, K. Nishitani, K. Sumitani, T. Oku, M. Sakai, Minoru Noda, M. Otsubo
Publikováno v:
IEEE Transactions on Electron Devices. 39:494-499
The authors have realized 16-kb SRAMs with maximum address access time of less than 5 ns and typical power dissipation of less than 2 W at temperatures ranging from 25 degrees C to 100 degrees C. For the RAMs, they have developed a triple-level Au-ba
Publikováno v:
IEEE Journal of Solid-State Circuits. 26:1399-1406
A GaAs 4 K*4-b static-Ram (SRAM) with high speed and high reliability has been developed for practical systems. By adopting a novel basic circuit technique to the peripheral circuits, the RAM operates over a wide temperature range. By using a novel m
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:1232-1238
A GaAs 1 K*4-kb SRAM designed using a novel circuit technology is described. To reduce the temperature dependence and the scattering of the access time, it was necessary to increase the signal voltage swing and to reduce the leakage current in access
Publikováno v:
11th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium.
A GaAs 4 K*4 b SRAM (static RAM) with improved alpha particle immunity is presented. By using a novel circuit technology and a buried p-layer FET, the critical charge of the memory cell has been increased and the collected charge decreased. The soft
Publikováno v:
10th Annual IEEE (GaAs IC) Symposium, Gallium Arsenide Integrated Circuit. Technical Digest 1988..
The authors describe a GaAs 1 K*4 static random-access memory (SRAM) which has been designed using a novel circuit technology to reduce the scattering and the temperature dependence of the access time. To reduce the subthreshold leakage current in th
Autor:
M. Sakai, Hirozo Takano, S. Matsue, T. Oku, K. Nishitani, K. Sumitani, H. Makino, H. Nakano, M. Noda
Publikováno v:
12th Annual Symposium on Gallium Arsenide Integrated Circuit (GaAs IC).
A fully functional GaAs 16 K SRAM is realized with an address access time of 4.4 ns and a power dissipation of 2 W. In the fabrication process, a triple-level Au-based interconnection technology is developed to reduce the wiring length, which strongl
Publikováno v:
SAE Technical Paper Series.
The continuously increasing integration level and resultant "system-on-silicon" and customization trends in VLSI technology will have a significant impact on future automotive electronics. 'The microcomputer, which is the kernel semiconductor device
Autor:
K. Nishitani, K. Sumitani, Minoru Noda, M. Sakai, H. Nakano, T. Oku, Mutsuyuki Otsubo, H. Makino, S. Matsue
Publikováno v:
Extended Abstracts of the 1990 International Conference on Solid State Devices and Materials.
Akademický článek
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Publikováno v:
IEEE Journal of Solid-State Circuits. 13:607-611
A 64K dynamic MOS RAM organized as 16K words/spl times/4 bits has been realized by short-channel and single-level polysilicon gate technologies. The RAM uses 2 /spl mu/m effective channel length (L/SUB eff/), and 400 /spl Aring/ gate oxide film thick