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pro vyhledávání: '"S. Jeannot"'
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Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2021, 183, pp.108122. ⟨10.1016/j.sse.2021.108122⟩
INFOS2021 22th Conference on Insulating Films on Semiconductors
INFOS2021 22th Conference on Insulating Films on Semiconductors, Jun 2021, Rende, Italy
Solid-State Electronics, Elsevier, 2021, 183, pp.108122. ⟨10.1016/j.sse.2021.108122⟩
INFOS2021 22th Conference on Insulating Films on Semiconductors
INFOS2021 22th Conference on Insulating Films on Semiconductors, Jun 2021, Rende, Italy
We propose a physical model of complementary resistive switching (CRS) based on the disruption and reformation process of a metallic filament inside each Oxyde Resistive Random Access Memory (OxRRAM) composing the CRS. The driving forces involved in
Autor:
Bruno Lee Sang, Patrick Harvey-Collard, Marina Labalette, G. Droulers, Serge Ecoffey, Stephane Monfray, Abdelkader Souifi, Dominique Drouin, S. Jeannot, Michel Pioro-Ladrière
Publikováno v:
Journal of Nanomaterials, Vol 2017 (2017)
Journal of Nanomaterials
Journal of Nanomaterials, Hindawi Publishing Corporation, 2017, 2017, pp.1-8. ⟨10.1155/2017/8613571⟩
Journal of Nanomaterials
Journal of Nanomaterials, Hindawi Publishing Corporation, 2017, 2017, pp.1-8. ⟨10.1155/2017/8613571⟩
We present a versatile nanodamascene process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon t
Autor:
A. Benoist, S. Bernasconi, G. Audoit, C. Guedj, Philippe Candelier, C. Fenouillet-Beranger, T. Dewolf, L. Perniola, E. Jalaguier, S. Jeannot, C. Charpin, Stephane Denorme, E. Vianello, M. Azzaz, Daniele Garbin, C. Cagli
Publikováno v:
Solid-State Electronics. 125:182-188
In this article, the reliability of HfO2-based RRAM devices integrated in an advanced 28 nm CMOS 16 kbit demonstrator is presented. In order to improve the memory performance, a thin Al2O3 layer is inserted in the HfO2-based memory stack (TiN/Ti/HfO2
Autor:
Philippe Boivin, Jean-Paul Barnes, Jean Coignus, Mickael Gros-Jean, S. Jeannot, F. Gaillard, I. Bottala-Gambetta, Nicolas Vaxelaire, Laurent Grenouillet, J. Ferrand, Etienne Nowak, T. Francois, Marc Bocquet, P. Chiquet
Publikováno v:
2019 IEEE 11th International Memory Workshop (IMW)
2019 IEEE 11th International Memory Workshop (IMW), May 2019, Monterey, United States. pp.1-4, ⟨10.1109/IMW.2019.8739664⟩
2019 IEEE 11th International Memory Workshop (IMW), May 2019, Monterey, United States. pp.1-4, ⟨10.1109/IMW.2019.8739664⟩
International audience; A clear comparison between Atomic Layer Deposition and Ion Implantation Si doping techniques is established. Comparable remnant polarization and coercive fields are obtained at lower Si content (%Si) for Ion Implantation, with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e400979c5b1a725c8889f66cc1ba58cb
https://hal.science/hal-02399691/document
https://hal.science/hal-02399691/document
Autor:
Boubacar Traore, Helen Grampeix, Philippe Blaise, Luca Perniola, Yoshio Nishi, Elisa Vianello, S. Jeannot, Barbara De Salvo
Publikováno v:
IEEE Transactions on Electron Devices. 62:4029-4036
We study in detail the impact of alloying HfO2 with Al (Hf1– x Al2 x O2+ x ) on the oxide-based resistive random access memory (RRAM) (OxRRAM) thermal stability through material characterization, electrical measurements, and atomistic simulation. I
Autor:
Adam Dobri, Alain Toffoli, Luca Perniola, F. Balestra, Fausto Piazza, S. Jeannot, Dann Morillon, C. Jahan
Publikováno v:
2017 EUROSOI-ULIS Proceedings
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.117-119, ⟨10.1109/ULIS.2017.7962616⟩
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Apr 2017, Athens, Greece. pp.117-119, ⟨10.1109/ULIS.2017.7962616⟩
session 9: Novel Materials and Technologies; International audience; Embedded flash memories having high-k metal gate-based logic devices will require modifications to the flash cells in order to remain economically feasible. One potential integratio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a43c0a93a1cbfb2a6566ce3dda23ad8c
https://hal.archives-ouvertes.fr/hal-02014190
https://hal.archives-ouvertes.fr/hal-02014190
Publikováno v:
Microelectronics Reliability
Microelectronics Reliability, Elsevier, 2017, 69, pp.47-51. ⟨10.1016/j.microrel.2016.12.006⟩
Microelectronics Reliability, 2017, 69, pp.47-51. ⟨10.1016/j.microrel.2016.12.006⟩
Microelectronics Reliability, Elsevier, 2017, 69, pp.47-51. ⟨10.1016/j.microrel.2016.12.006⟩
Microelectronics Reliability, 2017, 69, pp.47-51. ⟨10.1016/j.microrel.2016.12.006⟩
International audience; The silicon dioxide/silicon nitride/silicon dioxide (ONO) inter-gate dielectric layer has long been used in floating gate flash memories to provide coupling with the control gate, while simultaneously blocking leakage to it Gi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::01ee48b0b7b8fcf1e9e0b09db2fd63c6
https://hal.archives-ouvertes.fr/hal-02003020
https://hal.archives-ouvertes.fr/hal-02003020
Autor:
Yann Beilliard, Serge Ecoffey, Abdelkader Souifi, Marina Labalette, Serge Blonkowski, Dominique Drouin, S. Jeannot
Publikováno v:
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2017, 16 (5), pp.745-751. ⟨10.1109/TNANO.2017.2698205⟩
IEEE Transactions on Nanotechnology, Institute of Electrical and Electronics Engineers, 2017, 16 (5), pp.745-751. ⟨10.1109/TNANO.2017.2698205⟩
This paper presents the fabrication, together with morphological and electrical characterizations of complementary resistive switches using the nanodamascene process. The as-fabricated devices are fully embedded in an insulating oxide, opening the wa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::db0c91f25d4956757844b0f84e045438
https://hal.archives-ouvertes.fr/hal-01701505
https://hal.archives-ouvertes.fr/hal-01701505
Publikováno v:
2016 IEEE Nanotechnology Materials and Devices Conference (NMDC).
This paper proposes the fabrication, together with morphological and electrical characterizations of complementary resistive switches using a nanodamascene process. Complementary switches electrical performance are coherent with ReRAM fabricated and