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Theory of the structural phase transition in SrTiO3

Autor: Koji Harada, Wataru Kinase, S. Inumiya

Publikováno v: Ferroelectrics. 169:27-38

Phase transition of SrTiO3 is discussed by taking account of the interionic forces, namely, Coulomb, van der Waals' and overlap interactions among the constituent ions. It is concluded that the structural phase transition in SrTiO3 can be explained b

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2f76b2724c17585fc121d84964d0428e
https://doi.org/10.1080/00150199508217312

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A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Autor: James H. Stathis, Andreas Kerber, R. Divakaruni, Yue Hu, Hemanth Jagannathan, Dae-Gyu Park, Siddarth A. Krishnan, Richard Carter, Deleep R. Nair, Yun-Yu Wang, Ricardo A. Donaton, William K. Henson, Shahab Siddiqui, Ernest Y. Wu, Murshed M. Chowdhury, Kathy Barla, Huiming Bu, Mukesh Khare, Rohit Pal, J.-P. Han, Matthew W. Stoker, S. Saroop, Sufi Zafar, Michael P. Chudzik, Eduard A. Cartier, X. Chen, Jin Cai, Vamsi Paruchuri, Eric C. Harley, Myung-Hee Na, Dimitris P. Ioannou, Ryosuke Iijima, Min Dai, Kevin McStay, Takashi Ando, Joseph F. Shepard, J. Schaeffer, J-H Lee, Naim Moumen, P. Montanini, Lisa F. Edge, Paul D. Agnello, Shreesh Narasimha, Srikanth Samavedam, Dechao Guo, Unoh Kwon, Dominic J. Schepis, Yue Liang, Martin Ostermayr, S. Inumiya, Thomas A. Wallner, B. Greene, H. Yamasaki, D.P. Prakash, Jaeger Daniel, Stephen W. Bedell, M. Hargrove, Michael A. Gribelyuk, Gauri Karve, Y. Lee, Vijay Narayanan, S. Uchimura, Martin M. Frank

Publikováno v: 2011 International Electron Devices Meeting.

Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafer

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d662cd649e124b99bca46657dff7712f
https://doi.org/10.1109/iedm.2011.6131628

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A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process

Publikováno v: 2008 IEEE International Electron Devices Meeting.

For the first time, we demonstrate standard cell gate density of 3650 KGate/mm2 and SRAM cell of 0.124 mum2 for 32 nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7eb86e67686bfb13ad57ca9b67b74180
https://doi.org/10.1109/iedm.2008.4796776

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High-k/metal gate stack technology for advanced CMOS

Autor: Yasuo Nara, Y. Ohji, F. Ootsuka, S. Inumiya

Publikováno v: 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.

In order to obtain high performance CMOS devices with scaled dimensions, introduction of new technologies into the front-end fabrication process are required and therefore technologies such as strained channel, metal gate, high-k gate dielectrics, th

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::deb9f4df5583babce10d00226d1ed0df
https://doi.org/10.1109/icsict.2006.306252

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Reduction of threshold voltage deviation in Damascene metal gate MOSFETs

Autor: A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, K. Matsuo, Y. Akasaka, Y. Ozawa, H. Yano, G. Minamibaba, Y. Matsui, Y. Tsunashima, K. Suguro, T. Arikado, K. Okumura

Publikováno v: International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

The Damascene metal gate transistors are found to exhibit characteristics superior to those of the conventional polysilicon gate transistors with respect to the threshold voltage deviation (/spl Delta/V/sub th/) and the subthreshold swing (S-factor)

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::64b62690f9432c58353d9d4a9621e781
https://doi.org/10.1109/iedm.1999.823892

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HfSiON gate dielectric for CMOS applications

Autor: A. Nishiyama, Katsuyuki Sekine, R. Iijima, S. Inumiya, M. Takayanagi, T. Watanabe, I. Hirano, Y. Tsunashima, Akio Kaneko, K. Eguchi

Publikováno v: Extended Abstracts of International Workshop on Gate Insulator (IEEE Cat. No.03EX765).

In this paper, we review our results on HfSiON deposited by MOCVD. Characteristics of capacitors and FETs fabricated by the conventional poly-Si gate CMOS process are discussed. We cover the issues of flatband voltage shift, effective inversion-layer

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::97550c38b69d394f22b1d14d583e27bc
https://doi.org/10.1109/iwgi.2003.159199

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High performance metal gate MOSFETs fabricated by CMP for 0.1 μm regime

Autor: A. Yagishita, T. Saito, K. Nakajima, S. Inumiya, Y. Akasaka, Y. Ozawa, G. Minamihaba, H. Yano, K. Hieda, K. Suguro, T. Arikado, K. Okumura

Publikováno v: International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

We propose a plasma and thermal damage-free gate process named the "Damascene gate process" where CMP (Chemical Mechanical Polishing) is used in forming the gate structure. By using this process, fully planarized high performance metal (W/TiN or Al/T

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::200558a1df2a27cc7d837276e6b5ef85
https://doi.org/10.1109/iedm.1998.746473

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