Zobrazeno 1 - 10
of 19
pro vyhledávání: '"S. F. Tzou"'
Autor:
P. L. Cheng, Li-Shian Jeng, C. I. Liao, C. C. Chien, C. L. Yang, S. F. Tzou, Osbert Cheng, Cheng Tung Huang, Wensyang Hsu, Shyh-Fann Ting
Publikováno v:
Materials Chemistry and Physics. 107:471-475
Locally strained Si technology using embedded SiGe has been used to improve pMOSFET device performance through hole mobility enhancement. Embedded SiGe is achieved by selectively growing epitaxial SiGe film in recessed Si pMOSFET source and drain are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3965ee33a905ec766939def8560d07d0
https://doi.org/10.1016/j.matchemphys.2007.08.020
https://doi.org/10.1016/j.matchemphys.2007.08.020
Autor:
Keh-Ching Huang, Jinsong Tang, T. Fu, R. Kodali, Chan-Lon Yang, S. F. Tzou, V.C. Chang, Yonah Cho, Yi Cheng Chen, Hsiang-Ying Wang, L. Washington, Chin-Cheng Chien, Po-Lun Cheng, Chin-I Liao
Publikováno v:
Semiconductor Science and Technology. 22:S140-S143
Cyclical wet clean in DI-O 3 /SC1/DHF and low temperature bake in HCl/H 2 are presented as effective surface treatments for selective SiGe epitaxial deposition used to fabricate embedded SiGe pMOSFETs. The presented methods are most effective for dev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9d2f791db19a397d193a14d8ca6ab0e8
https://doi.org/10.1088/0268-1242/22/1/s33
https://doi.org/10.1088/0268-1242/22/1/s33
Autor:
Errol Antonio C. Sanchez, S. F. Tzou, Yonah Cho, Yi Cheng Chen, Tony Fu, Chan Lon Yang, Wen S. Hsu, Chin Cheng Chien, Vincent C Chang, Chin I. Liao, Hou Ren Wu, Po Lun Cheng, Jinsong Tang
Publikováno v:
ECS Transactions. 3:245-248
A thin layer (15A) of Si seed was employed to help nucleate low temperature selective SiGe epitaxial film in recessed source and drain. In combination with pre-epi wet clean and low temperature chemical bake, use of Si seed resulted in improved SiGe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3abb14ca3135690195248a5a079a05bc
https://doi.org/10.1149/1.2355817
https://doi.org/10.1149/1.2355817
Publikováno v:
2008 IEEE/SEMI Advanced Semiconductor Manufacturing Conference.
We proposed a novel method (DBB: Designed Based Binning) by using design and defect inspection information to detect marginal design features. This method was used to identify a pattern failure problem (hammer head) which occurred during production e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d986dca32ddcb3813fc12f1705effb7a
https://doi.org/10.1109/asmc.2008.4528996
https://doi.org/10.1109/asmc.2008.4528996
Publikováno v:
SPIE Proceedings.
As design rules continue to shrink beyond the lithography wavelength, pattern printability becomes a significant challenge in fabrication for 45nm and beyond. Model-based OPC and DRC checkers have been deployed using metrology data such as CD to fine
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1039cda9158e20172c09e2d9b0ef0405
https://doi.org/10.1117/12.772242
https://doi.org/10.1117/12.772242
Publikováno v:
2007 15th International Conference on Advanced Thermal Processing of Semiconductors.
Carbon and fluorine co-implantation have shown encouraging junction formation improvement, especially for P-type junctions. Nevertheless, no obvious improvement is found for arsenic implants. In this paper, phosphorous with different co-implants show
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d77134ae72843566dd4aa1de5e5bd3ab
https://doi.org/10.1109/rtp.2007.4383831
https://doi.org/10.1109/rtp.2007.4383831
Publikováno v:
SPIE Proceedings.
As critical dimensions shrink to fit advanced process generation requirements, line width roughness (LWR) has become more and more important. As design rules for semiconductor devices shrink, the line width roughness approaches the CD of the line its
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce54a6f2884283cda3312d8e894249e7
https://doi.org/10.1117/12.712537
https://doi.org/10.1117/12.712537
Autor:
Jack Jau, Wei-Yih Wu, Chan Lon Yang, Mingsheng Tsai, J. H. Yeh, S. F. Tzou, Y. D. Yang, Hong-Chi Wu, Shuen Cheng Lei, Hermes Liu, J. Y. Kao, Hong Xiao
Publikováno v:
SPIE Proceedings.
Dark voltage contrast (DVC) defects are detected on normally bright tungsten plugs (W-plugs) during the in-line e-beam inspection step. Cross-sectional scanning electron microscope (SEM) and transmission electron microscope (TEM) in a failure analysi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bda6649296264c95f18f3929727e1d77
https://doi.org/10.1117/12.656217
https://doi.org/10.1117/12.656217
Autor:
C. C. Chien, K. T. Huang, Andrzej Buczkowski, S. F. Tzou, Zhiqiang Li, Steve Hummel, Tom Walker, Chin I Liao
Publikováno v:
Photon Processing in Microelectronics and Photonics V.
Selective area epitaxial (SAE) growth of strained SiGe:B (Boron) in the recessed source/drain (S/D) region of an MOS device is known to improve Si-PMOS performance due to enhancement of hole mobility and reduction of S/D resistance. However, the proc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c55cf9ca1476d256352dc296f72495fe
https://doi.org/10.1117/12.645605
https://doi.org/10.1117/12.645605
Publikováno v:
SPIE Proceedings.
This paper describes the application of the Carrier Illumination technique to non-destructively measure dopant behavior before and after annealing for 65nm technology. Patterned wafers were implanted with different SDE energy and dosages. The detecte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7cd3b55331f66b292f9a99fd54c7a0dc
https://doi.org/10.1117/12.646050
https://doi.org/10.1117/12.646050