Zobrazeno 1 - 10
of 18
pro vyhledávání: '"S. Bordez"'
Publikováno v:
Solid-State Electronics. 53:127-133
For the first time, a huge drain current fluctuations degradation is shown on heavily pocket-implanted above-micrometer devices. This degradation, which is a serious concern for analog design, is attributed to the high potential barriers that stand a
Publikováno v:
2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
For the first time, a strong current local fluctuations degradation on heavily pocket-implanted long devices is shown. This degradation, which is a serious concern for analog design, is attributed to the high potential barriers that stand at end side
Publikováno v:
2008 IEEE International Conference on Microelectronic Test Structures.
Many test structures embedded in various technologies were measured to study the spacing impact on MOSFET mismatch. This impact is showed to highly depend on technology, device family, device type and bias conditions. The study of spatial correlation
Publikováno v:
2007 IEEE International Conference on Microelectronic Test Structures.
Delivering mismatch data that reflect design reality is a real challenge. Indeed, from test structures to final data utilization, many steps can be the source of distortion. The first possible source of distortion is linked to the differences in term
Publikováno v:
2007 IEEE International Conference on Microelectronic Test Structures.
MOS transistor threshold voltage matching is usually modeled proportionally to reverse square root of gate area. Yet this model is not satisfactory when discontinuities are observed. In this paper, a continuous matching model with only two parameters
Publikováno v:
AIP Conference Proceedings.
The aim of this work is to evaluate the impact on low frequency noise performances due to pocket implantation. Low frequency noise measurements have been done on different gate lengths in a range of 0.04 to 10 μm and 10 μm for gate width. Different
Autor:
N. Cave, Vincent Huard, C. Monget, C. Le Cam, S. Zoll, S. Parihar, S. Bordez, F. Guyader, D. Delille, N. Auriac, Michel Haond, R. Pantel, B. Icard, M. Zaleski, S. Harrison, A. Margain, C. Blanc, Scott Warrick, D. Barge, J. Belledent, D. Villanueva, Francois Leverd, G. Ribes, E. Baylac, Alexis Farcy, C. Laviron, Kathy Barla, E. Perrin, K. Rochereau, M. Bidaud, S. Manakli, Pascal Gouraud, Laurent Pain, O. Callen, Blandine Minghetti, Emmanuel Josse, Paulo Ferreira, R. Ranica
Publikováno v:
2006 International Electron Devices Meeting.
This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k di
Publikováno v:
2006 IEEE International Conference on Microelectronic Test Structures.
An improved methodology for the characterization of matching parameters in MOSFETs and bipolar transistors is presented. Because of their statistical nature, only estimation of matching parameters can be provided from given measurements. Considering
Publikováno v:
Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2005..
Matching of bipolar transistors has been characterized for high currents. The predominant impact of access resistance mismatch is clearly demonstrated, and matching models are suggested. Moreover, matching results dependency on test configurations is
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