Zobrazeno 1 - 10
of 94
pro vyhledávání: '"S. Baudot"'
Autor:
Joseph Ervin, Toby Hopf, S. Baudot, A. Soussou, Benjamin Vincent, Pieter Weckx, Steven Demuynck, A. P. Milenin, S. Wang
Publikováno v:
Advances in Patterning Materials and Processes XXXVI
In 5 nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24 nm. Fin depopulation is mandatory to enable the area scaling, but it becomes challenging at small pitches. In the first part, each process f
Autor:
Roger Loo, Robert Langer, Marc Schaekers, Erik Rosseel, John Tolle, Anurag Vohra, Clement Porret, Joe Margetis, S. Baudot, Lucas P. B. Lima, Giordano Scappucci, Bernardette Kunert, Janusz Bogdanowicz, J. F. Gomez Granados, Bastien Douhard, David Kohen, Amir Sammak, Andriy Hikavyy
Publikováno v:
ECS Journal of Solid State Science and Technology, 8(8)
ECS Transactions, 7, 86, 163-175
ECS Transactions, 7, 86, 163-175
As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::26e8763d24d466f7a51c61a11fd750d3
http://resolver.tudelft.nl/uuid:5be94773-fe68-4086-8d57-12b781c4a1c3
http://resolver.tudelft.nl/uuid:5be94773-fe68-4086-8d57-12b781c4a1c3
Autor:
F. Bertin, Olivier Renault, C. Dubourdieu, Blanka Detlefs, F. Pierre, Eugénie Martinez, R. Boujamaa, S. Baudot, Mickael Gros-Jean, Jörg Zegenhagen
Publikováno v:
Applied Surface Science
Applied Surface Science, Elsevier, 2015, 335, pp.71-77. ⟨10.1016/j.apsusc.2015.02.022⟩
Applied Surface Science, 2015, 335, pp.71-77. ⟨10.1016/j.apsusc.2015.02.022⟩
Applied Surface Science, Elsevier, 2015, 335, pp.71-77. ⟨10.1016/j.apsusc.2015.02.022⟩
Applied Surface Science, 2015, 335, pp.71-77. ⟨10.1016/j.apsusc.2015.02.022⟩
International audience; In this paper, we report the effect of high temperature annealing on the chemical and electronic structure of technologically relevant TiN/LaOx/HfSiON/SiON/Si gate stacks. Using medium energy ion scattering from the backside o
Autor:
Mathieu Charbonnier, C. Leroux, Gerard Ghibaudo, S. Baudot, P. Caubet, G. Reimbold, A. Toffoli, P. Blaise, A. Van Der Geest, F. Martin
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2013, 88, pp.21-26. ⟨10.1016/j.sse.2013.04.011⟩
Solid-State Electronics, 2013, 88, pp.21-26. ⟨10.1016/j.sse.2013.04.011⟩
Solid-State Electronics, Elsevier, 2013, 88, pp.21-26. ⟨10.1016/j.sse.2013.04.011⟩
Solid-State Electronics, 2013, 88, pp.21-26. ⟨10.1016/j.sse.2013.04.011⟩
The impact of additives (La, Al and Mg) at the SiO2/high-κ interface has been investigated through ab initio simulations and electrical measurements. Various gate stacks with additive below or the above high-κ dielectric are compared. Combination o
Autor:
Konstantin Bourdelle, B. Previtali, David Cooper, P. Scheiblin, C. Tabone, Cecile Aulnette, M. Valenza, F. Allain, Mikael Casse, Jean-Francois Damlencourt, J. Gyani, Bich-Yen Nguyen, L. Brevard, Christophe Figuet, Pierre Perreau, Olivier Weber, S. Baudot, Nicolas Daval, C. Le Royer, Francois Andrieu, C. Rauer
Publikováno v:
Solid-State Electronics. :9-15
We report an original Dual Strained Channel On Insulator (DSCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/c-SiGe/(s)SOI with a TiN/HfO 2 gate stack (EOT = 1.15 nm) and down to 40 nm gate lengths. We demonstrate
Autor:
P. Caubet, P. Normandon, C. Leroux, Mickael Gros-Jean, Gerard Ghibaudo, Roland Pantel, R.A. Bianchi, R. Boujamaa, S. Baudot, S. Zoll, Magali Gregoire
Publikováno v:
Microelectronic Engineering. 88:569-572
The MOSFET gate length reduction down to 32nm requires the introduction of a metal gate and a high-K dielectric as gate stack, both stable at high temperature. Here we use a nanometric layer of Lanthanum to shift the device threshold voltage from 500
Publikováno v:
Solid-State Electronics
Solid-State Electronics, Elsevier, 2010, 54 (9), pp.861-869. ⟨10.1016/j.sse.2010.04.032⟩
Solid-State Electronics, 2010, 54 (9), pp.861-869. ⟨10.1016/j.sse.2010.04.032⟩
Solid-State Electronics, Elsevier, 2010, 54 (9), pp.861-869. ⟨10.1016/j.sse.2010.04.032⟩
Solid-State Electronics, 2010, 54 (9), pp.861-869. ⟨10.1016/j.sse.2010.04.032⟩
International audience; Fully depleted silicon-on-insulator (FDSOI) n and pMOSFETs (Metal–Oxide–Semiconductor-Field-Effect-Transistors) are integrated with a TiN/HfO2 gate stack on 1.55 GPa strained SOI (sSOI) and 2.1 GPa eXtremely strained SOI (
Autor:
Olivier Weber, O. Faynot, S. Baudot, D. Lafond, T. Salvetat, L. Tosti, P. Perreau, L. Brevard, J.-F. Damlencourt, Francois Andrieu, Joël Eymery, S. Barnola
Publikováno v:
IEEE Electron Device Letters. 31:1074-1076
Strained p-MOSFETs with recessed and embedded silicon-germanium (eSiGe) source/drain (S/D) are fabricated on either silicon-on-insulator (SOI) or strained SOI (sSOI) substrates of 15-nm body thickness. For a gate voltage overdrive of -1 V and a gate
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We report on the quantitative determination of the strain map in a strained Silicon-On-Insulator (sSOI) line with a 200x70 nm^2 cross-section. In order to study a single line as a function of time, we used an X-ray nanobeam with relaxed coherence pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ca926ec20b1ce6532ceb40e7cd01a627