Zobrazeno 1 - 10
of 64
pro vyhledávání: '"S. Basker"'
Autor:
Jingyun Zhang, Ruqiang Bao, Ernest Y. Wu, Richard G. Southwick, Miaomiao Wang, Dechao Guo, Tian Shen, Huimei Zhou, Veeraraghavan S. Basker
Publikováno v:
IRPS
Time dependent dielectric breakdown (TDDB) reliability is studied on interfacial layer (IL)/high-K gate stack of Gate-All-Around Nanosheet (GAA-NS) N- and P-type Field Effect Transistors (FETs) with volume-less multiple threshold voltage (multi-Vt) i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1910c12dbdccbac0b7b5fbbcb1a75f09
https://doi.org/10.1109/irps46558.2021.9405204
https://doi.org/10.1109/irps46558.2021.9405204
Autor:
Tao Li, Chris A. Mack, Frougier Julien, Andrew M. Greene, Daniel J. Dechene, Chris Waskiewicz, Veeraraghavan S. Basker, Jingyun Zhang, Stuart A. Sieg, Carl J. Radens, Prateek Hundekar, Tsung-Sheng Kang, Indira Seshadri, Nelson Felix, Jennifer Church, Eric R. Miller, Mary Breton
Publikováno v:
Extreme Ultraviolet (EUV) Lithography XII.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ecd35b8cc836ad368baf97505bac549a
https://doi.org/10.1117/12.2583897
https://doi.org/10.1117/12.2583897
Autor:
Curtis Durfee, Frougier Julien, Daniel Schmidt, Andrew M. Greene, Veeraraghavan S. Basker, Jennifer Church, Nelson Felix, Indira Seshadri, Mary Breton
Publikováno v:
Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV.
Over the past several years, stacked Nanosheet Gate-All-Around (GAA) transistors captured the focus of the semiconductor industry and has been identified as the new lead architecture to continue LOGIC CMOS scaling beyond-5nm node. The fabrication of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c6a4ecf9f0ad6d25b631e6567243b1c
https://doi.org/10.1117/12.2583636
https://doi.org/10.1117/12.2583636
Autor:
Ruilong Xie, Heng Wu, Muthumanickam Sankarapandian, Dechao Guo, Huiming Bu, Balasubramanian S. Haran, Jingyun Zhang, Prasad Bhosale, Su-Chen Fan, Shogo Mochizuki, Zuoguang Liu, Andrew M. Greene, Jean E. Wynne, Frougier Julien, Nicolas Loubet, Veeraraghavan S. Basker, Shanti Pancharatnam
Publikováno v:
2020 IEEE International Interconnect Technology Conference (IITC).
An analysis of NanoSheet (NS) transistor parasitic resistance components is presented and correlated to the resistance readout on Si wafers. With this model, it is possible to identify which components cause the parasitic resistance increases as CPP
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bb66210a04273bfa45f8a15fb4f60f60
https://doi.org/10.1109/iitc47697.2020.9515644
https://doi.org/10.1109/iitc47697.2020.9515644
Autor:
Daniel Schmidt, Igor Turovets, Veeraraghavan S. Basker, Andrew M. Greene, Frougier Julien, Mary Breton, Aron Cepler, Marjorie Cheng, Dexin Kong, Nicolas Loubet, Mark Klare, Roy Koret, Jingyun Zhang, Abraham Arceo de la Pena, Ishtiaq Ahsan
Publikováno v:
2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
The methodology of measuring the lateral etch, or indentation, of SiGe nanosheets by using optical scatterometry, x-ray fluorescence, and machine learning algorithms is presented and discussed. Stacked nanosheet device structures were fabricated with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3f7a2fb31f627b7d8b01b43a56fe6d4
https://doi.org/10.1109/asmc49169.2020.9185226
https://doi.org/10.1109/asmc49169.2020.9185226
Autor:
Erin Stuckert, Tian Shen, Andrew M. Greene, Veeraraghavan S. Basker, Jingyun Zhang, Miaomiao Wang, Huimei Zhou, Michael P. Belyansky, Koji Watanabe
Publikováno v:
IRPS
For stacked Nanosheet gate-all-around transistors, a new failure mode between the gate and epitaxial source/drain (PC-Epi) is introduced in the Middle-Of-Line (MOL) intermetal dielectrics (IMD) because of a unique module called inner spacer. In this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b461cfd24ebd85ab4415a8d7ae23b731
https://doi.org/10.1109/irps45951.2020.9129258
https://doi.org/10.1109/irps45951.2020.9129258
Autor:
Pietro Montanini, Stuart A. Sieg, Andrew M. Greene, Nelson Felix, Xu Wenyu, Daniel J. Dechene, Jingyun Zhang, Eric R. Miller, Yann Mignot, Carl J. Radens, Indira Seshadri, Praveen Joseph, Veeraraghavan S. Basker, Mary Breton, Tao Li
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIV.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c1657e32b8611133cff6f9ccc289143
https://doi.org/10.1117/12.2552159
https://doi.org/10.1117/12.2552159
Autor:
Andrew M. Greene, Aelan Mosden, Peter Biolsi, Cheryl Alix, Jeffrey Smith, Veeraraghavan S. Basker, Subhadeep Kal, Daniel Schmidt, Michael P. Belyansky, Koji Watanabe, Frougier Julien, Shanti Pancharatnam, Nicolas Loubet, Jingyun Zhang, Flaugh Matthew, Dechao Guo, Kai Zhao, Huimei Zhou, Maruf Bhuiyan, Balasubramanian S. Haran, Chanemougame Daniel, Miaomiao Wang, Curtis Durfee, Huiming Bu, Ivo Otto, Mary Breton
Publikováno v:
ECS Meeting Abstracts. :943-943
Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::2fba30178f3e31c0a43256dbe4a6242d
https://doi.org/10.1149/ma2021-0230943mtgabs
https://doi.org/10.1149/ma2021-0230943mtgabs
Autor:
Vimal Kamineni, Junli Wang, Susan Su Chen Fan, Andre Labonte, Ruilong Xie, Dinesh Gupta, Raja Muthinti, Juntao Li, Dechao Guo, Ryan Kevin J, B. Peethala, Richard Conte, Christopher Prindle, Veeraraghavan S. Basker, Shanti Pancharatnam, Kangguo Cheng, Albert M. Young, Stan D. Tsai, Huiming Bu, H. P. Amanapu, Chanro Park, Balasubramanian S. Haran, Robert R. Robison, Nicolas Loubet, Y. Liang, Huimei Zhou, Kisik Choi, Richard A. Conti, Andreas Knorr, Cave Nigel, Adra Carr, Saraf Iqbal Rashid, Andrew M. Greene, Michael P. Belyansky, Hao Tang, Mark Raymond
Publikováno v:
2019 Symposium on VLSI Technology.
We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both g
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ddd686fefd2d3d87577b75e554a2b83f
https://doi.org/10.23919/vlsit.2019.8776492
https://doi.org/10.23919/vlsit.2019.8776492
Autor:
Kerem Akarvardar, Balasubramanian S. Haran, Dinesh Gupta, Juntao Li, Takashi Ando, Economikos Laertis, James J. Demarest, Andreas Knorr, Kai Zhao, Victor Chan, Ruqiang Bao, Cave Nigel, Huimei Zhou, Richard A. Conti, Veeraraghavan S. Basker, Andrew M. Greene, Huiming Bu, Miaomiao Wang, Robert R. Robison, Kanakasabapathy Sivananda K, Indira Seshadri, Chanro Park, Dechao Guo, Muthumanickam Sankarapandian, Ruilong Xie, Liying Jiang
Publikováno v:
2019 Symposium on VLSI Technology.
In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which redu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c79d17d97f0f8e79a50e6f8d02ad91d6
https://doi.org/10.23919/vlsit.2019.8776493
https://doi.org/10.23919/vlsit.2019.8776493