Zobrazeno 1 - 10
of 74
pro vyhledávání: '"S. Aritome"'
Autor:
H. Fijita, S. Aritome, Y. Sakamoto, Ching Yuan Ho, Chenhsin Lien, Y. M. Lin, C. H. Liu, Ru Jye Yang, S. Pittikoun
Publikováno v:
IEEE Electron Device Letters. 29:1199-1202
In this letter, plasma nitridation and oxidation on interpoly dielectric (IPD; SiO2-SiN-SiO2 ) for cell programming speed and reliabilities are investigated. Nitrided top oxide with N2 plasma shows excellent physical and electrical properties in term
Autor:
H. P. Hwang, S. Pittikoun, S. Aritome, Shin-Hsien Chen, Houng-Chi Wei, C. H. Liu, G. H. Tseng, C. M. Chao, Y. M. Lin, D. Y. Yin, H. W. Liaw
Publikováno v:
2009 IEEE International Memory Workshop.
The various methods of multi-nitridation ONO to improve NAND flash memory have been demonstrated in this paper. Excellent cell performance and reliability are obtained compared to convention ONO: (1) 1.9 V program voltage reduction owing to 23 A EOT
Autor:
Shin-Hsien Chen, H. P. Hwang, P. J. Chiang, D. Y. Yin, C. Y. Ho, C. H. Hung, Y. Sakamoto, S. Aritome, R. J. Yang, C. H. Liu, S. Pittikoun, H. C. Wei, Y. M. Lin
Publikováno v:
2009 International Symposium on VLSI Technology, Systems, and Applications.
Multi-Nitridation ONO has been demonstrated for the first time. Significant improvement are obtained in NAND Flash performance and reliability. (1) 1V program voltage reduction owing to 10A EOT (equivalant oxide thickness ) reduction (2) More than 20
Publikováno v:
International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).
This paper describes a novel scaled and low-voltage-operation NAND EEPROM technology with a G_ate-O_ffset NAND C_ell (GOC-NAND), which is free from program disturbance in a self-boosted program. In GOC-NAND, novel source/drain engineering is introduc
Autor:
K. Imamiya, Y. Sugiura, H. Nakamura, T. Himeno, K. Takeuchi, T. Ikehashi, K. Kanda, K. Hosono, R. Shirota, S. Aritome, K. Shimizu, K. Hatakeyama, K. Sakui
Publikováno v:
1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
Publikováno v:
1996 Symposium on VLSI Technology. Digest of Technical Papers.
The read disturb degradation caused by source erase is studied. The anomalous Vth shift of about 1.0 V due to electron trapping is observed during read disturb. Vth shift due to electron trapping is more serious for high speed erase device. However,
Autor:
K. Shimizu, K. Narita, H. Watanabe, E. Kamiya, Y. Takeuchi, T. Yaegashi, S. Aritome, T. Watanabe
Publikováno v:
International Electron Devices Meeting. IEDM Technical Digest.
This paper describes a novel high density 5F/sup 2/ (F: feature size) NAND STI cell technology which has been developed for a low bit-cost flash memories. The extremely small cell size of 0.31 /spl mu/m/sup 2/ has been obtained for the 0.25 um design
Autor:
K. Hatakeyama, T. Maruyama H. Watanabe, T. Yamaguchi, S. Aritome, Koji Sakui, Tetsuo Endoh, Susumu Shuto, Gertjan Hemink, H. Iizuka, Toshihiro Tanaka, Riichiro Shirota, Masaki C O Patent Div Momodomi
Publikováno v:
Extended Abstracts of the 1993 International Conference on Solid State Devices and Materials.
Publikováno v:
28th International Reliability Physics Symposium.
Autor:
Ching Yuan Ho, Chenhsin Lien, Y. Sakamoto, Ru Jye Yang, Hiro Fijita, C. H. Liu, Y. M. Lin, S. Pittikoun, S. Aritome
Publikováno v:
IEEE Electron Device Letters; Nov2008, Vol. 29 Issue 11, p1199-1202, 4p, 5 Graphs