Zobrazeno 1 - 5
of 5
pro vyhledávání: '"S. A. Smolov"'
Publikováno v:
Труды Института системного программирования РАН, Vol 29, Iss 4, Pp 247-256 (2018)
Hardware testing is a process aimed at detecting manufacturing faults in integrated circuits. To measure test quality, two main metrics are in use: fault detection abilities (fault coverage) and test application time (test length). Many algorithms ha
Externí odkaz:
https://doaj.org/article/ae31f53688d8405d8aa9f9eb5848aa0d
Autor:
S. A. Smolov
Publikováno v:
Труды Института системного программирования РАН, Vol 27, Iss 1, Pp 97-124 (2018)
In this paper a survey of existing methods of model extraction from hardware system descriptions written in Hardware Description Languages (like Verilog and VHDL) is presented. There are many tasks in hardware and software design where models are app
Externí odkaz:
https://doaj.org/article/7ebafb9ee2e5449b8cd27ec4711a1c50
Autor:
M. S. Lebedev, S. A. Smolov
Publikováno v:
Труды Института системного программирования РАН, Vol 28, Iss 4, Pp 41-56 (2018)
Automated test generation is a promising direction in hardware verification research area. Functional test generation methods based on models are widespread at the moment. In this paper, a functional test generation method based on model checking is
Externí odkaz:
https://doaj.org/article/db5cd6bc2a3c4fd88d1b58c262c5cfae
Autor:
S. A. Smolov, M. S. Lebedev
Publikováno v:
Труды Института системного программирования РАН, Vol 28, Iss 4, Pp 41-56 (2018)
Automated test generation is a promising direction in hardware verification research area. Functional test generation methods based on models are widespread at the moment. In this paper, a functional test generation method based on model checking is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a6c66847f2c2bc2ec8bafce6c6f094ef
https://ispranproceedings.elpub.ru/jour/article/view/138
https://ispranproceedings.elpub.ru/jour/article/view/138
Autor:
S. A. Smolov
Publikováno v:
Труды Института системного программирования РАН, Vol 27, Iss 1, Pp 97-124 (2018)
In this paper a survey of existing methods of model extraction from hardware system descriptions written in Hardware Description Languages (like Verilog and VHDL) is presented. There are many tasks in hardware and software design where models are app
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e91ecfb40cd3a6d7c71924e96ac2a1e8
https://doi.org/10.15514/ispras-2015-27(1)-6
https://doi.org/10.15514/ispras-2015-27(1)-6