CAT platform for analogue and mixed-signal test evaluation and optimization

Autor: Ahcène Bounceur, Salvador Mir, Emmanuel Simeu, Luis Rolindez

Publikováno v: VLSI-SoC: Research trends in VLSI and Systems on Chip
G. De Micheli, S. Mir, R. Reis. VLSI-SoC: Research trends in VLSI and Systems on Chip, Springer, pp.280-300, 2007, IFIP International Federation for Information Processing
VLSI-SoC: Research trends in VLSI and Systems on Chip, G. De Micheli, S. Mir, R. Reis (Ed.), pp.280-300, 2007
Proceedings on 14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC'06)
14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC'06)
14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC'06), 2006, Nice, France. pp.320-325
14th IFIP International Conference on Very Larage Scale Integration (VLSI-SoC'06), May 2006, France. pp.0
IFIP International Federation for Information Processing ISBN: 9780387749082
VLSI-SoC (Selected Papers)

ISBN : 978-0-387-74908-2; This paper introduces a Computer-Aided-Test platform that has been developed for the evaluation of test techniques for analogue and mixed-signal circuits. The CAT platform, integrated in the Cadence Design Framework Environm

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fac847cc8b9811709837db3a8f659543
https://hal.archives-ouvertes.fr/hal-00202160